Metal gate of gate-all-around transistor

Patent metadata

Field	Value
Publication number	US-9786774-B2
Application number	US-201414318377-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness.

First claim

What is claimed is:

1. A semiconductor device comprising:
a nanowire structure comprising a channel region between a source region and a drain region;
a first isolation region over the source region;
a second isolation region adjacent the source region and the first isolation region;
a gate dielectric over the first isolation region and the second isolation region; and
a metal gate surrounding a portion of the channel region, the metal gate comprising:
a first gate portion contacting a top surface of the gate dielectric, the first gate portion having a vertical region and a horizontal region, the vertical region having a first thickness, the horizontal region disposed over the first isolation region and the second isolation region; and
a second gate portion over the first gate portion, the second gate portion having a second thickness less than the first thickness.

2. The semiconductor device of claim 1 , wherein a ratio of the first thickness to the second thickness is from 1.5 to 10.

3. The semiconductor device of claim 1 , wherein the first gate portion has a first height and the second gate portion has a second height equal to or greater than the first height.

4. The semiconductor device of claim 3 , wherein a ratio of the first height to the second height is from 0.1 to 1.

5. The semiconductor device of claim 1 , wherein the first gate portion has a first height and the second gate portion has a second height less than the first height.

6. The semiconductor device of claim 5 , wherein a ratio of the first height to the second height is from 1.5 to 10.

7. The semiconductor device of claim 1 , wherein a cross-sectional shape of the second gate portion comprises a square, rectangular, or triangular shape.

8. The semiconductor device of claim 1 , wherein the first gate portion and the second gate portion are a contiguous same material.

9. A semiconductor device comprising:
a first nanowire transistor comprising:
a first nanowire structure comprising a first channel region between a first source region and a first drain region, and
a first metal gate surrounding a portion of the first channel region, the first metal gate comprising:
a first gate portion adjacent to the first source region having a first thickness, and
a second gate portion adjacent to the first drain region having a second thickness less than the first thickness; and

a second nanowire transistor comprising:
a second nanowire structure comprising a second channel region between a second source region and a second drain region, and
a second metal gate surrounding a portion of the second channel region, the second metal gate having a uniform thickness.

10. The semiconductor device of claim 9 , wherein a ratio of the first thickness to the second thickness is from 1.5 to 10.

11. The semiconductor device of claim 9 , wherein the first gate portion has a first height and the second gate portion has a second height equal to or greater than the first height.

12. The semiconductor device of claim 11 , wherein a ratio of the first height to the second height is from 0.1 to 1.

13. The semiconductor device of claim 9 , wherein the first gate portion has a first height and the second gate portion has a second height less than the first height.

14. The semiconductor device of claim 13 , wherein a ratio of the first height to the second height is from 1.5 to 10.

15. The semiconductor device of claim 9 , wherein the first metal gate comprises Al, Ti, or TiN.

16. The semiconductor device of claim 9 , wherein a cross-sectional shape of the second gate portion comprises a square, rectangular, or triangular shape.

17. The semiconductor device of claim 9 , wherein the first thickness is substantially equal to the uniform thickness.

18. A semiconductor device comprising:
a drain region;
a source region;
a channel region between the drain region and the source region; and
a metal gate surrounding a portion of the channel region, the metal gate comprising:
a neck region proximate the drain region, the neck region having a first region with a first width and a second region with a second width greater than the first width, wherein the neck region is a first material; and
a shoulder portion proximate the source region, the shoulder portion having a third width greater than the first width and the second width, wherein the shoulder portion is the first material.

19. The semiconductor device of claim 18 , wherein the neck region and the shoulder portion is an integral piece.

20. The semiconductor device of claim 18 , wherein a ratio of the second width to the first width is from 1.5 to 10.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean-Pierre
• Liu Chi-Wen

Classifications

• H01L29/66469

  Electricity · mapped topic

• H01L29/0676

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66439

  Electricity · mapped topic

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title