Thin-substrate double-base high-voltage bipolar transistors

Patent metadata

Field	Value
Publication number	US-9786773-B2
Application number	US-201614992971-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Jan 9, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide). Very high breakdown voltage, and fast turn-off, are achieved with very small on-resistance.

First claim

What is claimed is, among others (and, without exclusion, in addition to any other points which are indicated herein as inventive and/or surprising and/or advantageous):

1. A power semiconductor device which includes:
both an n-type emitter/collector region, and also a p-type base contact region, on each of both first and second surfaces of a p-type semiconductor die; wherein each said emitter/collector region is positioned to act as an emitter of a bidirectional switch while the other emitter/collector region acts as a collector thereof;
wherein the material of the semiconductor die has a bandgap greater than two eV;
and wherein the rated OFF voltage of the device, divided by the resistivity of the semiconductor die in ohm-cm, and further divided by the thickness in microns of the die between the emitter/collector regions on the first and second surfaces, yields a value greater than two amps per cm-μm;
wherein the base contact region on the first surface is not electrically connected to the base contact region on the second surface, except through the semiconductor die itself; and
wherein the emitter/collector region on the first surface is not electrically connected to the emitter/collector region on the second surface, except through the semiconductor die itself.

2. The device of claim 1 , wherein the semiconductor die is silicon carbide.

3. A power semiconductor device which includes:
both a first-conductivity-type emitter/collector region, and also a second-conductivity-type base contact region, on each of both first and second surfaces of a second-conductivity-type silicon carbide semiconductor die;
and wherein the rated OFF voltage of the device, divided by the resistivity of the semiconductor die in ohm-cm, and further divided by the thickness in microns of the die between the emitter/collector regions on the first and second surfaces, yields a value greater than two amps per cm-μm;
wherein the base contact region on the first surface is not electrically connected to the base contact region on the second surface, except through the semiconductor die itself; and
wherein the emitter/collector region on the first surface is not electrically connected to the emitter/collector region on the second surface, except through the semiconductor die itself.

4. The device of claim 3 , wherein the semiconductor die is p-type.

Assignees

• Ideal Power Inc
• Ideal Power Inc

Inventors

• Alexander William C

Classifications

• H03K17/567

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H01L29/1608

  Electricity · mapped topic

• H01L29/747 Primary

  Electricity · mapped topic

• H03K17/74

  by the use, as active elements, of diodes (by the use of more than one type of semiconductor device H03K17/567; by the use of tunnel diodes H03K17/58; by the use of negative resistance diodes H03K17/70) · CPC title

• H01L29/72

  Electricity · mapped topic