Complementary tunneling FET devices and method for forming the same

Patent metadata

Field	Value
Publication number	US-9786769-B2
Application number	US-201315036058-A
Country	US
Kind code	B2
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

First claim

I claim:

1. A tunneling field effect transistor (TFET), comprising:
a substrate;
a doped first region, disposed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table;
a doped second region, disposed above the substrate, having transparent or semi-transparent oxide n-type semiconductor material; and

a gate stack coupled to the doped first and second regions.

2. The TFET of claim 1 , wherein the transparent or semi-transparent oxide n-type semiconductor material is selected from a group consisting of α-Ga 2 —O 3 , β-Ga 2 —O 3 , In 2 O 3 , and SnO 2 .

3. The TFET of claim 1 , wherein the TFET is a FinFET, Tri-Gate, or square nano-wire based device.

4. The TFET of claim 1 further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the first and second doped regions from one another.

5. The TFET of claim 1 further comprises a lightly doped p-type material coupled to the gate stack, the lightly doped p-type material separating the first and second doped regions from one another.

6. The TFET of claim 1 , wherein the doped first region is a source region, and wherein the doped second region is a drain region.

Assignees

• Intel Corp

Inventors

• Aleksov Aleksandar

Classifications

• H01L29/7391

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L51/0037

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L21/8258

  Electricity · mapped topic