Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9786676-B2
Application number	US-201615217313-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	Nov 10, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
a channel on the substrate, the channel extending in a first direction perpendicular to an upper surface of the substrate;
a dummy channel on the substrate, the dummy channel extending from the upper surface of the substrate in the first direction;
a plurality of gate electrodes spaced apart from each other in the first direction at a plurality of levels, respectively, on the substrate, each of the gate electrodes surrounding outer sidewalls of the channel and the dummy channel, the channel and the dummy channel contacting each other between the upper surface of the substrate and a first gate electrode among the gate electrodes, the first gate electrode being at a lowermost one of the levels; and
a support pattern between the upper surface of the substrate and the first gate electrode.

2. The vertical memory device of claim 1 , wherein a width of the dummy channel is greater than a width of the channel.

3. The vertical memory device of claim 1 , wherein the support pattern includes one of silicon-germanium and doped polysilicon.

4. The vertical memory device of claim 1 , wherein the support pattern vertically overlaps a portion of the first gate electrode.

5. The vertical memory device of claim 1 , further comprising:
a plurality of support patterns on the substrate between the substrate and the first electrode, wherein
the plurality of support patterns include the support pattern.

6. The vertical memory device of claim 5 , wherein the plurality of support patterns are arranged under the first gate electrode.

7. The vertical memory device of claim 1 , wherein
the channel includes a first extension portion and a first expansion portion,
the first extension portion extends in the first direction; and
the first expansion portion is expanded from a lower portion of the first extension portion in a direction parallel to the upper surface of the substrate,
the first expansion portion has a width greater than a width of the first extension portion,
the dummy channel includes a second extension portion and a second expansion portion,
the second extension portion extends in the first direction; and
the second expansion portion is expanded from a lower portion of the second extension portion in the direction parallel to the upper surface of the substrate, the second expansion portion has a width greater than a width of the second extension portion, and
the first and second expansion portions contact each other between the upper surface of the substrate and the first gate electrode.

8. The vertical memory device of claim 1 , further comprising:
an epitaxial layer on the substrate between the upper surface of the substrate and the first gate electrode.

9. The vertical memory device of claim 1 , further comprising an etch stop pattern between the first gate electrode and the support pattern.

10. The vertical memory device of claim 1 , wherein the channel includes a plurality of channels spaced apart from each other, and the dummy channel includes a plurality of dummy channels spaced apart from each other.

11. A vertical memory device, comprising:
a plurality of gate electrodes on a substrate, the plurality of gate electrodes being spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
a channel on the substrate and extending in the first direction through the gate electrodes;
a dummy channel on the substrate and extending in the first direction from the upper surface of the substrate through the gate electrodes, a lower portion of the dummy channel contacting a lower portion of the channel;
a first contact plug on the channel;
a first wiring electrically connected to the channel through the first contact plug;
a second contact plug on the dummy channel; and
a second wiring electrically connected to the dummy channel through the second contact plug.

12. The vertical memory device of claim 11 , further comprising:
a second capping pattern between the dummy channel and the second contact plug, wherein
the second capping pattern is doped with p-type impurities.

13. The vertical memory device of claim 12 , further comprising:
a first capping pattern between the channel and the first contact plug, wherein
the first capping pattern is doped with n-type impurities.

14. The vertical memory device of claim 11 , wherein the dummy channel has a width greater than a width of the channel.

15. The vertical memory device of claim 11 , wherein
each of the channel and the dummy channel includes an expansion portion between the upper surface of the substrate and a first gate electrode among the gate electrodes,
the expansion portion of the channel has a width greater than a width of other portions of the channel,
the expansion portion of the dummy channel has a width greater than a width of the dummy channel,
the first gate electrode is a lowermost one of the gate electrodes, and
the expansion portions of the channel and the dummy channel contact each other.

16. A vertical memory device, comprising:
a substrate;
a plurality of gate electrodes stacked on top of each other on the substrate, the gate electrodes defining channel holes that extend through the gate electrodes in a first direction perpendicular to an upper surface of the substrate, the channel holes being spaced apart from each other in a second direction and a third direction that cross each other and are parallel to the upper surface of the substrate;
a support pattern between the upper surface of the substrate and the gate electrodes, the support pattern defining channel openings that connect to the channel holes; and
a plurality of channel structures filling the channel holes and the channel openings, the channel structures extending in the first direction through the gate electrodes, a portion of each of the channel structures extending in the third direction in the channel openings.

17. The vertical memory device of claim 16 , further comprising:
dummy channel structures on the substrate, wherein
the gate electrodes define dummy channel holes spaced apart from the channel holes,
the support pattern defines dummy channel openings that connect to the dummy channel holes,
the dummy channel structures fill the dummy channel holes and dummy channel openings, and
the dummy channel structures contact corresponding channel structures between the upper surface of the substrate and a lowermost one of the gate electrodes, wherein
the dummy channel structures contact corresponding channel structures between the upper surface of the substrate and a lowermost one of the gate electrodes.

18. The vertical memory device of claim 16 , wherein a width of the dummy channel holes is greater than a width of the channel holes.

19. The vertical memory device of claim 16 , further comprising:
an epitaxial layer on the substrate, wherein
the epitaxial layer is between the upper surface of the substrate and a lowermost one of the gate electrodes, and
the epitaxial layer contacts the channel structures to electrically connect the channel structures to the substrate.

20. The vertical memory device of claim 16 , further comprising:
insulation layers between the gate electrodes, wherein
the support layer includes a material having an etching selectivity with respect to the insulation layers and the substrate.

Assignees

• Yun Jang-Gn
• Xia Zhiliang
• Moon Ahn-Sik
• Park Se-Jun
• Lim Joon-Sung
• Hwang Sung-Min
• Samsung Electronics Co Ltd

Inventors

• Yun Jang-Gn
• Xia Zhiliang
• Moon Ahn-Sik
• Park Se-Jun
• Lim Joon-Sung
• Hwang Sung-Min

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic