Dual deep trenches for high voltage isolation

Patent metadata

Field	Value
Publication number	US-9786665-B1
Application number	US-201615238198-A
Country	US
Kind code	B1
Filing date	Aug 16, 2016
Priority date	Aug 16, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate having a top surface and a bottom surface;
a buried layer positioned within the substrate;
a transistor well region positioned above the buried layer;
a first trench extending from the top surface to penetrate the buried layer, the first trench having a first trench depth; and
a second trench extending from the top surface to penetrate the buried layer, the second trench interposed between the first trench and the transistor well region, and having a second trench depth less than the first trench depth,
wherein:
the first trench includes a first conductor insulated from the buried layer and making an ohmic contact with the substrate around a bottom portion of the first trench; and
the second trench includes a second conductor insulated from the buried layer and the substrate.

2. The integrated circuit of claim 1 , wherein the dielectric liner insulates the conductor to a floating state.

3. The integrated circuit of claim 1 , wherein the second trench includes a conductor structured to receive a bias voltage associated with a breakdown voltage of a junction between the buried layer and the substrate.

4. The integrated circuit of claim 1 , wherein the second trench includes a conductor structured to receive a bias voltage associated with an electric field density threshold of a junction between the buried layer and the substrate.

5. The integrated circuit of claim 1 , wherein the first trench is spaced apart from the second trench by a distance associated with a breakdown voltage of a junction between the buried layer and the substrate.

6. The integrated circuit of claim 1 , wherein the first trench is spaced apart from the second trench by a distance associated with an electric field density threshold of a junction between the buried layer and the substrate.

7. The integrated circuit of claim 1 , wherein the first trench is spaced apart from the second trench by a distance greater than 1 um.

8. The integrated circuit of claim 1 , wherein the first trench has a first aperture defined at the top surface, and the second trench has a second aperture defined at the top surface and smaller than the first aperture.

9. The integrated circuit of claim 1 , further comprising:
a high voltage circuit developed outside of the transistor well region; and
a low voltage circuit developed within of the transistor well region and shield from the high voltage circuit by the first trench and the second trench.

10. An integrated circuit, comprising:
a substrate having a first conductivity type, a top surface, and a bottom surface;
a buried layer having a second conductivity type opposite of the first conductivity type, the buried layer positioned in the substrate;
a transistor well region positioned above the buried layer;
a first trench extending from the top surface to penetrate the buried layer, the first trench having: a first trench depth, and a first conductor insulated from the buried layer and making an ohmic contact with the substrate around a bottom portion of the first trench; and
a second trench extending from the top surface to penetrate the buried layer, the second trench interposed between the first trench and the transistor well region, and having: a second trench depth less than the first trench depth, and a second conductor insulated from the buried layer and the substrate.

11. The integrated circuit of claim 10 , wherein the second conductor is insulated to a floating state.

12. The integrated circuit of claim 10 , wherein the second conductor is structured to receive a bias voltage associated with a breakdown voltage of a junction between the buried layer and the substrate.

13. The integrated circuit of claim 10 , wherein the second conductor is structured to receive a bias voltage associated with an electric field density threshold of a junction between the buried layer and the substrate.

14. The integrated circuit of claim 10 , wherein the first trench is spaced apart from the second trench by a distance associated with a breakdown voltage of a junction between the buried layer and the substrate.

15. The integrated circuit of claim 10 , wherein the first trench is spaced apart from the second trench by a distance associated with an electric field density threshold of a junction between the buried layer and the substrate.

16. A method, comprising:
forming a buried layer within a substrate;
forming a transistor well region above the buried layer;
forming a first trench extending from a top surface of the substrate to penetrate the buried layer, the first trench having a first trench depth;
forming a second trench extending from the top surface of the substrate to penetrate the buried layer, the second trench interposed between the first trench and the transistor well region, and having a second trench depth less than the first trench depth;
forming a first conductor within the first trench, the first conductor insulated from the buried layer and making an ohmic contact with the substrate around a bottom portion of the first trench; and
forming a second conductor within the second trench, the second conductor insulated from the buried layer and the substrate.

17. The method of claim 16 , further comprising:
insulating the second conductor to a floating state.

18. The method of claim 16 , further comprising:
forming a conductor within the second trench;
forming a contact with the conductor for receiving a bias voltage associated with a breakdown voltage of a junction between the buried layer and the substrate.

19. The method of claim 16 , wherein the first trench is spaced apart from the second trench by a distance associated with a breakdown voltage of a junction between the buried layer and the substrate.

20. The method of claim 16 , wherein the first trench is spaced apart from the second trench by a distance associated with an electric field density threshold of a junction between the buried layer and the substrate.

21. The method of claim 16 , wherein the first trench is spaced apart from the second trench by a distance greater than 1.5 um.

22. The method of claim 16 , wherein:
the forming the first trench includes:
defining a first aperture at the top surface of the substrate; and
etching a top layer of the substrate, the buried layer, and a bottom layer of the substrate for a predetermined time period through the first aperture; and
the forming the second trench includes:
defining a second aperture at the top surface of the substrate, the second aperture smaller than the first aperture; and

etching the top layer of the substrate, the buried layer, and the bottom layer of the substrate for the predetermined time period through the second aperture.

23. The method of claim 16 , further comprising:
forming a high voltage circuit outside of the transistor well region; and
forming a low voltage circuit within of the transistor well region and shielded from the high voltage circuit by the first trench and the second trench.

Assignees

• Texas Instruments Inc

Inventors

• Pendharkar Sameer
• Hu Binghua
• Sadovnikov Alexei
• Mathur Guru

Classifications

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title