Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-9786625-B2
Application number	US-201514803138-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Mar 14, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate having first and second major surfaces, wherein the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending through the base substrate from the first to the second major surface of the package substrate;
an adhesive disposed on and covering a top surface of the base substrate, wherein the via contacts extend above the top surface of the base substrate and the adhesive is about aligned to sides of the via contacts;
an insulating layer having first and second major surfaces, wherein the insulating layer is disposed directly over the adhesive and the via contacts;
a plurality of conductive studs disposed within the insulating layer, wherein the conductive studs extend from the first to the second major surface of the insulating layer, wherein a width of the conductive studs is smaller than a width of the via contacts;
conductive traces disposed directly on the first major surface of the insulating layer and over the conductive studs;
a die having conductive contacts on its first or second surfaces disposed on the package substrate, wherein the conductive contacts of the die are electrically coupled to the conductive traces; and
a cap disposed over the package substrate and encapsulates the die, wherein a bottom of the cap contacts the conductive traces and the first major surface of the insulating layer.

2. The semiconductor package of claim 1 wherein the insulating layer electrically isolates the plurality of conductive studs from each other, wherein a top surface of the conductive studs is coplanar to the first major surface of the insulating.

3. The semiconductor package of claim 2 wherein the second major surface of the insulating layer partially covers and contacts a top surface of the via contacts.

4. The semiconductor package of claim 2 wherein the second major surface of the insulating layer contacts the adhesive and the via contacts.

5. The semiconductor package of claim 1 wherein the conductive traces are coupled to the conductive studs, wherein the conductive studs couple the conductive traces to the via contacts, wherein the via contacts, the conductive studs and the conductive traces correspond to interconnect structures of the package substrate.

6. The semiconductor package of claim 5 wherein the conductive studs comprise a multi-layered stack having at least a first conductive layer and a second conductive layer different from the first conductive layer.

7. The semiconductor package of claim 6 wherein the first conductive layer comprises a nickel layer and the second conductive layer comprises a copper layer and the second conductive layer contacts the via contacts.

8. The semiconductor package of claim 5 wherein the via contacts correspond to a first interconnect level, wherein the conductive studs correspond to a second interconnect level, wherein the conductive traces correspond to a third interconnect level, wherein the first, second and third interconnect levels define the interconnect structures of the package substrate.

9. The semiconductor package of claim 1 wherein the adhesive comprises a UV sensitive laminate material.

10. The semiconductor package of claim 1 wherein the width of the conductive studs is defined by a circumference of the conductive studs and the width of the via contacts is defined by a circumference of the via contacts, wherein one or more of the conductive studs are disposed directly on a top surface of the via contact and do not extend laterally beyond the width of the via contact.

11. The semiconductor package of claim 1 comprising package contacts disposed on a bottom surface of the base substrate, wherein the package contacts are coupled to a bottom of the via contacts.

12. The semiconductor package of claim 11 wherein the package contacts protrude downwardly from the bottom surface of the base substrate.

13. The semiconductor package of claim 1 wherein the conductive studs comprise a same conductive material as the via contacts.

14. The semiconductor package of claim 13 wherein the conductive traces comprise a same conductive material as the conductive studs.

15. The semiconductor package of claim 1 wherein the insulating layer is disposed between and separates the conductive traces from the adhesive.

16. A semiconductor package comprising:
a package substrate having a top and a bottom surface, wherein the package substrate comprises a base substrate having a mold material and a plurality of via contacts, wherein the via contacts extend through the base substrate from the top surface to the bottom surface of the package substrate;
an adhesive disposed on and covering a top surface of the base substrate, wherein the via contacts extend above the top surface of the base substrate and the adhesive abuts sides of the via contacts;
an insulating layer having first and second major surfaces, wherein the insulating layer is disposed directly on the adhesive, wherein the second major surface of the insulating layer contacts a top surface of the via contacts;
a plurality of conductive studs disposed within the insulating layer, wherein the conductive studs extend from the first to the second major surface of the insulating layer, wherein a width of the conductive studs is smaller than a width of the via contacts;
conductive traces disposed directly on the insulating layer and over the conductive studs;
a die mounted on the package substrate;
a cap disposed over the package substrate and encapsulates the die; and
wherein a bottom of the cap contacts the conductive traces and the insulating layer.

17. The semiconductor package of claim 16 wherein the die comprises conductive contacts, wherein the conductive contacts of the die are electrically coupled to the conductive traces on the insulating layer.

18. The semiconductor package of claim 16 wherein the insulating layer electrically isolates the plurality of conductive studs from each other, wherein the insulating layer separates the conductive traces from the via contacts and the adhesive.

19. The semiconductor package of claim 16 wherein the conductive studs comprise a multi-layered stack having at least a first conductive layer and a second conductive layer below the first conductive layer, wherein the first conductive layer contacts the conductive traces and comprises a conductive material different from the conductive traces and the via contacts.

20. The semiconductor package of claim 16 comprising package contacts which are directly coupled to a bottom surface of the via contacts, wherein the bottom surface of the via contacts are recessed relative to a bottom surface of the base substrate.

Assignees

• Utac Headquarters Pte Ltd
• United Test And Assembly Center Ltd

Inventors

• Yang Yongbo
• Dimaano Antonio Jr Bambalan
• Wo Chun Hong

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title