Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages

Patent metadata

Field	Value
Publication number	US-9786567-B2
Application number	US-201715414909-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Mar 13, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

First claim

What is claimed is:

1. A method for testing a package structure comprising:
electrically testing a first plurality of conductive connectors in a first package, wherein the first plurality of conductive connectors bonds a first package component to a second package component, and wherein the first package component comprises:
first testing structures on a first substrate; and
first functional circuitry on the first substrate and independent from the first testing structures; and

electrically testing a second plurality of conductive connectors in a second package, wherein the second plurality of conductive connectors bonds a third package component to a fourth package component, and wherein the third package component comprises:
second testing structures on a second substrate and having a same circuit layout as the first testing structures, wherein a first electrical signal sent through the first testing structures during electrically testing the first plurality of conductive connectors is a same signal as a second electrical signal sent through the second testing structures during electrically testing the second plurality of conductive connectors; and
second functional circuitry on the second substrate and independent from the second testing structures, wherein the second functional circuitry has a different circuit layout as the first functional circuitry.

2. The method of claim 1 , wherein the second package component comprises a first probing pad electrically connected to the first testing structures, wherein electrically testing the first plurality of conductive connectors comprises applying a universal testing probe card to the first probing pad.

3. The method of claim 2 , wherein the first probing pad is disposed in a region outside of a footprint of the first substrate in a top-down view.

4. The method of claim 2 , wherein the fourth package component comprises a second probing pad electrically connected to the second testing structures, wherein electrically testing the second plurality of conductive connectors comprises applying the universal testing probe card to the second probing pad.

5. The method of claim 1 , wherein the first testing structures are disposed in a center region of the first package component.

6. The method of claim 1 , wherein the first testing structures are disposed in a corner region of the first package component.

7. The method of claim 1 further comprising after electrically testing the first plurality of conductive connectors, physically examining at least a subset of the first plurality of conductive connectors using an x-ray.

8. The method of claim 1 , wherein the first testing structures comprise a daisy chain, a kelvin structure, or a combination thereof.

9. A method comprising:
bonding a first package component to a second package component using a first plurality of conductive bumps, wherein the first package component comprises:
first testing structures comprising first test bumps and a first plurality of electrically interconnected conductive lines electrically connected to the first test bumps; and
first functional circuitry on a same substrate as the first testing structures and independent from the first testing structures;

bonding a third package component to a fourth package component using a second plurality of conductive bumps, wherein the third package component comprises:
second testing structures comprising second test bumps and a second plurality of electrically interconnected conductive lines electrically connected to the second test bumps, wherein the first plurality of electrically interconnected conductive lines and the second plurality of electrically interconnected conductive lines have a same layout; and
second functional circuitry on a same substrate as the second testing structures and independent from the second testing structures, wherein the second functional circuitry and the first functional circuitry have different layouts;

electrically testing the first plurality of conductive bumps using the first testing structures; and
electrically testing the second plurality of conductive bumps using the second testing structures.

10. The method of claim 9 , wherein electrically testing the first plurality of conductive bumps and electrically testing the second plurality of conductive bumps comprises applying a same testing probe card to a first probing pad disposed on the second package component and a second probing pad disposed on the fourth package component.

11. The method of claim 9 , wherein a location of the first testing structures in the first package component is the same as a relative location of the second testing structures in the second package component.

12. The method of claim 9 , wherein the first testing structures are disposed in a central region of the first package component, a corner region of the first package component, or a combination thereof.

13. The method of claim 9 , wherein the first testing structures comprises a daisy chain, a kelvin structure, or a combination thereof.

14. The method of claim 9 , wherein electrically testing the first plurality of conductive bumps comprises sending a first test signal through the first plurality of conductive bumps, wherein electrically testing the second plurality of conductive bumps comprises sending a second test signal through the second plurality of conductive bumps, and wherein the first test signal and the second test signal are the same signal.

15. The method of claim 9 further comprising performing an x-ray test on the first plurality of conductive bumps.

16. A method comprising
providing a testing structure design, the testing structure design defining:
test bumps; and
a plurality of conductive lines electrically connected to the test bumps;

disposing a first package component in a first package, wherein the first package component comprises:
first testing structures in accordance with the testing structure design; and
first functional circuitry formed on a same substrate as the first testing structures and independent from the first testing structures; and

disposing a second package component in a second package, wherein the second package component comprises:
second testing structures in accordance with the testing structure design; and
second functional circuitry formed on a same substrate as the second testing structures and independent from the second testing structures, wherein the second functional circuitry and the first functional circuitry have different layouts.

17. The method of claim 16 , wherein the first package further comprises a third package component bonded to the first package component through a first plurality of conductive connectors, wherein the method further comprises electrically testing the first plurality of conductive connectors by sending a first test signal through the first testing structures.

18. The method of claim 17 , wherein the second package further comprises a fourth package component bonded to the second package component through a second plurality of conductive connectors, wherein the method further comprises electrically testing the second plurality of conductive connectors by sending a second test signal through the second testing structures, and wherein the first test signal is the same signal as the second test signal.

19. The method of claim 16 , wherein the testing structure design designates a relative location for placement of testing structures within a package component.

20. The method of claim 16 , wh

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Wei-Cheng
• Hsu Li-Han
• Chiu Sao-Ling
• Hou Shang-Yun
• Jeng Shin-Puu
• Lin Chen-Hua

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title