Methods of forming one or more covered voids in a semiconductor substrate

Patent metadata

Field	Value
Publication number	US-9786548-B2
Application number	US-201514712219-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Feb 7, 2007
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

First claim

The invention claimed is:

1. A method of forming a covered void in a semiconductor substrate, comprising:
providing a semiconductor substrate comprising exposed different first and second materials, the second material comprising a pair of projections projecting upwardly relative to the first material and comprising sidewalls;
providing an exposed third material atop the second material projections, the third material being different from the second material; and
relative to the second material, selectively growing additional first material from the exposed first material and selectively from the exposed third material to bridge across the pair of second material projections to form a covered void between the pair of projections, the selectively growing being at a rate of growth which is at least 2:1 compared to any rate of growth from the sidewalls of the second material for at least about 100 Angstroms of growth from the first material.

2. The method of claim 1 comprising providing the third material to be the same as the first material.

3. The method of claim 1 comprising providing the third material to be different from the first material.

4. The method of claim 1 comprising providing the first material to comprise monocrystalline elemental-form silicon, and the selectively growing comprises epitaxial silicon-comprising growth from the first material.

5. The method of claim 4 comprising providing the third material to comprise any one or more of elemental-form W, elemental-form Ti, or a silicide.

6. The method of claim 4 comprising providing the third material to comprise elemental-form silicon.

7. The method of claim 6 comprising providing the third material to comprise elemental-form amorphous silicon.

8. The method of claim 6 comprising providing the third material to comprise elemental-form monocrystalline silicon, and wherein the selectively growing comprises monocrystalline epitaxial silicon-comprising growth from the elemental-form monocrystalline silicon.

9. The method of claim 8 comprising providing a monocrystalline elemental-form silicon first material to comprise a <100> plane direction, the exposed elemental-form monocrystalline silicon third material comprising a <100> plane direction which is parallel that of the first material.

10. The method of claim 6 wherein the selectively growing comprises polysilicon-comprising growth from the third material.

11. The method of claim 1 comprising providing the third material to comprise elemental-form silicon, and the selectively growing comprises growing any one or more of elemental-form W or a silicide.

12. The method of claim 1 comprising providing the third material to comprise elemental-form silicon and elemental-form Ge.

13. The method of claim 1 comprising providing the third material to comprise Ga and As.

14. The method of claim 1 comprising providing the second material to be insulative.

15. The method of claim 14 comprising providing the second material to comprise at least one of silicon dioxide or silicon nitride.

16. The method of claim 1 comprising providing the second material to be conductive.

17. The method of claim 1 comprising providing the pair of projections to comprise walls of an opening.

18. The method of claim 17 comprising providing the opening to comprise an elongated trench running generally parallel a mean outermost global surface of the semiconductor substrate, the covered void being a covered trench.

19. The method of claim 18 comprising filling at least a majority of the covered trench with conductive material and forming an elongated conductive line therefrom.

20. The method of claim 1 comprising providing the pair of projections to comprise spaced free-standing pillars prior to said selectively growing.

21. The method of claim 20 comprising providing the pair of projections to comprise two of a plurality of spaced free-standing pillars prior to said selectively growing, the selectively growing forming the void to be covered by a ceiling supported at least in part by the plurality of pillars received within the void.

22. The method of claim 1 wherein the selectively growing is devoid of growing detectible first material from at least a majority of the second material sidewalls.

23. The method of claim 1 wherein the selectively growing comprises growing a semiconductive material, and further comprising providing field effect transistor source/drain regions within the selectively grown semiconductive material.

24. The method of claim 1 wherein the selectively growing comprises growing a semiconductive material, and further comprising providing a field effect transistor channel region within the selectively grown semiconductive material.

25. The method of claim 1 wherein the selectively growing is at a selectivity relative to the second material of at least ten to one.

26. The method of claim 1 wherein the selectively growing is at a selectivity relative to the second material of at least one hundred to one.

27. A method of forming a plurality of covered voids in a semiconductor substrate, comprising:
depositing insulative material over an elemental-form silicon-containing material;
depositing silicon over the insulative material;
etching a plurality of openings through the silicon and the insulative material to the elemental-form silicon-containing material; and
selectively growing relative to the insulative material an elemental-form silicon-comprising material from the elemental-form silicon-containing material and from the silicon to bridge across the plurality of openings to cover and not completely fill the plurality of openings to form the plurality of covered voids under the elemental-form silicon-comprising material that bridges across the plurality of openings, the selectively growing being at a rate of growth which is at least 2:1 compared to any rate of growth from the insulative material for at least about 100 Angstroms of growth from the elemental-form silicon-containing material.

28. The method of claim 27 wherein the silicon deposited over the insulative material is amorphous.

29. The method of claim 27 comprising after forming the plurality of covered voids by the selectively growing, at least partially filling the plurality of covered voids with solid material.

30. The method of claim 29 comprising only partially filling the plurality of covered voids with the solid material with the partially filled voids remaining in a final construction.

31. The method of claim 27 comprising after forming the plurality of covered voids by the selectively growing, completely filling the plurality of covered voids with solid material such that the voids do not exist in a final construction.

32. The method of forming a plurality of covered voids in a semiconductor substrate, comprising:
depositing insulative material over a first elemental-form silicon-containing material;
forming a second elemental-form silicon-containing material over the insulative material;
etching a plurality of openings through the second elemental-form silicon-containing material and the insulative material to the first elemental-form silicon-containing material;
epitaxially growing a first elemental-form silicon-comprising material from the first elemental-form silicon-containing mat

Assignees

• Micron Technology Inc

Inventors

• Wells David H

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title