Isolation structure of semiconductor device

Patent metadata

Field	Value
Publication number	US-9786543-B2
Application number	US-201514961573-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Mar 1, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a substrate;
epitaxially growing a first epitaxial material in the trench, wherein a lattice constant of the first epitaxial material is different from a lattice constant of the substrate;
forming a first dielectric layer over the first epitaxial material;
after forming the first dielectric layer, converting a portion of the first epitaxial material to a second dielectric layer interposed between the first dielectric layer and the first epitaxial material; and
after converting the portion of the first epitaxial material to the second dielectric layer, forming a third dielectric layer over the first dielectric layer, the third dielectric layer filling the trench, the third dielectric layer extending into the trench.

2. The method of claim 1 , further comprising, after forming the third dielectric layer:
recessing the substrate adjacent the trench; and
epitaxially growing a second epitaxial material on the substrate, the second epitaxial material having a different lattice constant than the substrate.

3. The method of claim 2 , further comprising recessing the first dielectric layer, the second dielectric layer, and the third dielectric layer.

4. The method of claim 3 , further comprising forming a gate stack over the second epitaxial material.

5. The method of claim 1 , wherein converting the portion of the first epitaxial material to the second dielectric layer includes an oxygen-containing plasma treatment using O 2 , O 3 , H 2 O, H 2 O 2 , NO, or N 2 O as an oxygen source gas.

6. The method of claim 1 , wherein the converting comprises forming an oxide of the first epitaxial material.

7. The method of claim 1 , further comprising, prior to epitaxially growing the first epitaxial material, performing a pre-clean process.

8. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a substrate;
epitaxially growing a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
forming a high-k dielectric layer over the strained material;
performing a treatment to form an oxide layer of the strained material between the high-k dielectric layer and the strained material; and
forming a dielectric layer over the high-k dielectric layer filling the trench.

9. The method of claim 8 , wherein performing the treatment to the substrate includes an oxygen-containing plasma treatment using O 2 , O 3 , H 2 O, H 2 O 2 , NO, or N 2 O as an oxygen source gas.

10. The method of claim 9 , wherein the oxygen-containing plasma treatment is performed under a pressure of about 1 Torr to about 10 Torr.

11. The method of claim 9 , wherein the oxygen-containing plasma treatment is performed under a source power of about 25 W to about 900 W.

12. The method of claim 8 , further comprising recessing the substrate to form a recess adjacent the trench and epitaxially growing another strained material on the substrate in the recess, the another strained material having a different lattice constant than the substrate.

13. The method of claim 12 , further comprising performing a planarization process after epitaxially growing the another strained material.

14. The method of claim 13 , further comprising:
recessing the high-k dielectric layer, the oxide layer, and the dielectric layer; and
forming a gate stack over the another strained material.

15. A method of fabricating a semiconductor device, the method comprising:
forming a first trench and a second trench in a substrate;
epitaxially growing a first epitaxial material in the first trench and the second trench, wherein a lattice constant of the first epitaxial material is different from a lattice constant of the substrate;
forming a first dielectric layer over the first epitaxial material;
forming a second dielectric layer of the first epitaxial material between the first dielectric layer and the first epitaxial material;
forming a third dielectric layer over the first dielectric layer; and
after forming the third dielectric layer, recessing the substrate between the first trench and the second trench.

16. The method of claim 15 , further comprising epitaxially growing a second epitaxial material over the substrate between the first trench and the second trench.

17. The method of claim 16 , further comprising recessing the first dielectric layer, the second dielectric layer, and the third dielectric layer.

18. The method of claim 17 , further comprising forming a gate dielectric over the second epitaxial material and a gate electrode over the gate dielectric, the first epitaxial material extending between the gate dielectric and the second epitaxial material.

19. The method of claim 18 , wherein forming the second dielectric layer is performed at least in part by using an oxygen-containing plasma treatment using O 2 , O 3 , H 2 O, H 2 O 2 , NO, or N 2 O as an oxygen source gas.

20. The method of claim 15 , further comprising recessing the first dielectric layer, the second dielectric layer, and the third dielectric layer below an upper surface of the first epitaxial material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Shu-Han
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13 Primary

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10P14/60 Primary

  of insulating materials · CPC title