Isolation structure of semiconductor device

Patent metadata

Field	Value
Publication number	US-9209066-B2
Application number	US-201313782105-A
Country	US
Kind code	B2
Filing date	Mar 1, 2013
Priority date	Mar 1, 2013
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

The invention relates to an isolation structure of a semiconductor device. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.

First claim

What is claimed is:

1. An isolation structure for a semiconductor device comprising:
a substrate comprising a trench;
a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein the strained material comprises an oxide layer of the strained material over a remainder of the strained material;
a high-k dielectric layer over the oxide layer; and
a dielectric layer over the high-k dielectric layer filling the trench, wherein a top surface of the strained material extends further away from a bottom of the trench than a top surface of the dielectric layer.

2. The isolation structure of claim 1 , wherein the strained material comprises Ge or Si 1-x Ge x .

3. The isolation structure of claim 1 , wherein the strained material has a thickness ranging from 1 nm to 500 nm.

4. The isolation structure of claim 1 , wherein the oxide layer of the strained material comprises SiO 2 or GeO 2 .

5. The isolation structure of claim 1 , wherein the high-k dielectric layer comprises Al 2 O 3 , ZrO 2 , HfO 2 , TaSiO x , LaHfO x , or La 2 O 3 .

6. The isolation structure of claim 1 , wherein the high-k dielectric layer has a thickness ranging from 0.1 nm to 3 nm.

7. The isolation structure of claim 1 , wherein the dielectric layer comprises silicon oxide, silicon nitride, silicon oxy-nitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material.

8. A fin field effect transistor (FinFET) comprising:
a substrate comprising a major surface and a trench higher than the major surface;
a fin structure protruding from the major surface adjacent to the trench;
a gate structure traversing over the fin structure; and
an isolation structure surrounding the fin structure, wherein the isolation structure comprises
a first strained material in the trench, wherein a lattice constant of the first strained material is different from a lattice constant of the substrate, and wherein a top layer of the first strained material comprises an oxide layer of the first strained material;
a high-k dielectric layer over the oxide layer; and
a dielectric layer over the high-k dielectric layer filling the trench, wherein a top surface of the first strained material is higher than a top surface of the dielectric layer.

9. The FinFET of claim 8 , wherein the fin structure comprises a second strained material, wherein a lattice constant of the second strained material is different from a lattice constant of the substrate.

10. The FinFET of claim 9 , wherein the second strained material comprises Ge or Si 1-x Ge x .

11. The FinFET of claim 8 , wherein the first strained material comprises Ge or Si 1-x Ge x .

12. The FinFET of claim 8 , wherein the first strained material has a thickness ranging from 1 nm to 500 nm.

13. The FinFET of claim 8 , wherein the oxide layer of the first strained material comprises SiO 2 or GeO 2 .

14. The FinFET of claim 8 , wherein the high-k dielectric layer comprises Al 2 O 3 , ZrO 2 , HfO 2 , TaSiO x , LaHfO x , or La 2 O 3 .

15. The FinFET of claim 8 , wherein the high-k dielectric layer has a thickness ranging from 0.1 nm to 3 nm.

16. The FinFET of claim 8 , wherein the dielectric layer comprises silicon oxide, silicon nitride, silicon oxy-nitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material.

17. An isolation structure for a semiconductor device comprising:
a trench having a bottom in a substrate defined by a major surface of a first semiconductor material and having sidewalls defined by fins extending from the major surface of the first semiconductor material;
the trench being filled with the following materials in the following order, starting at the bottom of the trench and continuing to the top of the trench:
a second semiconductor material, the second semiconductor material having a lattice constant unequal to the lattice constant of the first semiconductor material;
an oxide of the second semiconductor material;
a first dielectric layer; and
a second dielectric layer, wherein a top surface of the second semiconductor material extends further away from the bottom of the trench than a top surface of the second dielectric layer.

18. The isolation structure of claim 17 , wherein the first semiconductor material comprises one of silicon and silicon-germanium, and the second semiconductor material comprises the other of silicon and silicon-germanium.

19. The isolation structure of claim 17 , wherein the fins extending from the major surface of the semiconductor material include a lower portion comprising the first semiconductor material and an upper portion comprising a third semiconductor material having a lattice constant that differs from the lattice constant of the first semiconductor material.

20. The isolation structure of claim 17 further comprising a gate stack extending over the second dielectric layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Shu-Han
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13 Primary

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10P14/60 Primary

  of insulating materials · CPC title