Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

Patent metadata

Field	Value
Publication number	US-9786387-B2
Application number	US-201514729295-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Aug 26, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged; and
an error correcting code (ECC) circuit configured to,
generate parity data based on main data,
write a codeword including the main data and the parity data in the memory cell array,
read the codeword from a selected memory cell row to generate syndromes, and
correct errors using the parity data in the read codeword on a per symbol basis based on the syndromes, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first data and the second data being assigned to one symbol of a plurality of symbols, the first memory cell and the second memory cell being adjacent to each other in the memory cell array.

2. The semiconductor memory device of claim 1 ,
wherein the main data includes 2 p bits and the parity data includes q bits, where q is greater than p and p and q are natural numbers equal to or greater than two, and
wherein the ECC circuit is configured to generate q-bit check bits based on data in the read codeword, and generate the syndromes with q-bits based on the q-bit check bits and q-bit parity data in the read codeword.

3. The semiconductor memory device of claim 2 , wherein the ECC circuit is configured to correct the errors if the one symbol includes errors equal to or smaller than two.

4. The semiconductor memory device of claim 2 ,
wherein values of the q-bit syndromes are linearly independent in first through third cases, and
wherein the first case corresponds to a case when the first data has an error and the second data has no error, the second case corresponds to a case when the first data has no error and the second data has an error, and the third case corresponds to a case when the first data has an error and the second data has an error.

5. The semiconductor memory device of claim 2 , wherein the ECC circuit comprises:
an encoder configured to generate the parity data based on the main data; and
a decoder configured to generate the syndromes based on the read codeword to correct the errors.

6. The semiconductor memory device of claim 5 , wherein the encoder comprises a plurality of parity generators, each of the plurality of parity generators being configured to generate a corresponding parity bit of the q-bit parity data based on the 2 p -bit main data.

7. The semiconductor memory device of claim 5 , wherein the decoder comprises:
a check bit generator configured to generate the q-bit check bits based on the main data of the read codeword;
a syndrome generator configured to generate the q-bit syndromes based on the q-bit check bits and the parity data of the read codeword; and
a corrector configured to correct the errors in the read codeword based on the q-bit syndromes.

8. The semiconductor memory device of claim 7 , wherein the syndrome generator is configured to generate the syndromes such that each syndrome has a logic level according to whether corresponding bits of the q-bit check bits and the q-bit parity data are equal to each other.

9. The semiconductor memory device of claim 8 , wherein the syndrome generator includes a plurality of logic elements, each of the plurality of logic elements being configured to perform an XOR operation on corresponding bits of the q-bit check bits and the q-bit parity data to generate a corresponding syndrome.

10. The semiconductor memory device of claim 7 , wherein the corrector includes a plurality of unit correctors, and each of the plurality of unit correctors are configured to correct errors in each of the plurality of symbols on the per symbol basis if a number of the errors is equal to or smaller than two based on the syndromes.

11. The semiconductor memory device of claim 10 , wherein each of the unit correctors includes:
a symbol decoder configured to determine whether at least one of the first data and the second data has an error based on the syndromes to generate first through third output signals; and
a data corrector configured to correct errors in one of the plurality of symbols based on the first through third output signals.

12. The semiconductor memory device of claim 11 , wherein the symbol decoder includes:
a first sub decoder configured to provide the first output signal indicating whether the first data has an error based on the syndromes;
a second sub decoder configured to provide the second output signal indicating whether the second data has an error based on the syndromes; and
a third sub decoder configured to provide the third output signal indicating whether each of the first data and second data has an error based on the syndromes.

13. The semiconductor memory device of claim 11 , wherein the data corrector includes:
a first logic element configured to perform an OR operation on the first output signal and the second output signal;
a second logic element configured to perform an OR operation on the second output signal and the third output signal;
a third logic element configured to perform an XOR operation on the first data and an output of the first logic element to output a first corrected data; and
a fourth logic element configured to perform an XOR operation on the second data and an output of the second logic element to output a second corrected data.

14. The semiconductor memory device of claim 11 , wherein the data corrector is configured to invert the first data if the first data has an error, invert the second data if the second data has an error, and invert the first data and the second data if each of the first data and the second data has an error.

15. The semiconductor memory device of claim 1 , wherein each of the plurality of memory cells is a resistive type memory cell, and
wherein the memory cell array includes a three-dimensional memory array in which at least one of word-lines and bit-lines are shared between levels.

16. The semiconductor memory device of claim 1 , wherein first data of the first memory cell of the selected memory cell row and second data of the second memory cell of the selected memory cell row are assigned to a same symbol of the plurality of symbols.

17. The semiconductor memory device of claim 16 , wherein the first memory cell and the second memory cell are on a same word-line.

18. A device, comprising:
a decoder configured to,
receive a codeword from a selected memory cell row of a memory cell array, the received codeword including main data and parity data, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first memory cell and the second memory cell being adjacent to each other in the memory cell array, the first data and the second data being assigned to a first symbol of a plurality of symbols,
generate an error indicator for the first symbol based on the received codeword,
detect errors in the received codeword based on the error indicator, and

correct the detected errors in the received codeword using the parity data.

19. The device of claim 18 , wherein the decoder is configured to generate the error indicator based on the parity data and check bit data derived from the main data.

20. The device of claim 18 , wherein the decoder is configured to generate the error indicator for the first symbol by,
generating a first sub-error indicator for the first data,
generating a sec

Assignees

• Cha Sang-Uhn
• Chung Hoi-Ju
• Son Jong-Pil
• Park Kwang-Il
• Jang Seong-Jin
• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Chung Hoi-Ju
• Son Jong-Pil
• Park Kwang-Il
• Jang Seong-Jin

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/702

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title