Apparatuses and methods for performing logical operations using sensing circuitry

Patent metadata

Field	Value
Publication number	US-9786335-B2
Application number	US-201514725956-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	Jun 5, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array through a shift circuitry intermediate in the pair of complementary sense lines, and comprising:
a sense amplifier directly coupled to a pair of complementary sense lines via a first input node and a second input node; and
a compute component coupled to the sense amplifier and comprising a dynamic latch,

wherein the sensing circuitry is configured to: perform a logical operation; and initially store a result of the logical operation in the sense amplifier, and
wherein the shift circuitry is configured as a multiplexor capable of selecting from among at least 3 inputs to the sensing circuitry.

2. The apparatus of claim 1 , wherein the sensing circuitry is configured to perform the logical operation without transferring data via an input/output (I/O) line.

3. The apparatus of claim 1 , wherein the sensing circuitry is configured to perform the logical operation without transferring data to a control component external to the array.

4. The apparatus of claim 1 , wherein the sensing circuitry is further configured to retain an input data value in the dynamic latch unchanged by performance of the logical operation.

5. The apparatus of claim 1 , wherein the compute component comprises an accumulator.

6. The apparatus of claim 1 , wherein the shift circuitry is configured to connect the sensing circuitry to one of the pair of complementary sense lines and an adjacent pair of complementary sense lines.

7. The apparatus of claim 1 , wherein the shift circuitry is configured as a multiplexor capable of coupling to the sensing circuitry one of two pairs of adjacent complementary sense lines and the pair of complementary sense lines in an inverted configuration.

8. The apparatus of claim 1 , wherein the compute component further comprises a static latch coupled to the dynamic latch.

9. The apparatus of claim 1 , wherein, to perform an AND logical operation, the sensing circuitry is further configured to:
write a “0” data value to the sense amplifier unchanged when the dynamic latch reflects a “1” data value; and
leave a data value stored in the sense amplifier unchanged when the dynamic latch reflects a “1” data value.

10. The apparatus of claim 1 , wherein, to perform an OR logical operation, the sensing circuitry is further configured to:
write a “1” data value to the sense amplifier when the dynamic latch reflects a “1” data value; and
leave a data value stored in the sense amplifier unchanged when the dynamic latch reflects a “0” data value.

11. A method, comprising:
loading a first data value to a dynamic latch of a compute component coupled to an array of memory cells via a pair of complementary sense lines, wherein loading the first data value includes activating a first control signal associated with a load transistor of the compute component;
storing a second data value to a sense amplifier directly coupled to the compute component via the pair of complementary sense lines via a first input node and a second input node;
performing a particular logical operation using the first data value and the second data value, wherein performing the particular logical operation includes activating a second control signal associated with the particular logical operation; and
storing a result of the particular logical operation initially in the sense amplifier.

12. The method of claim 11 , wherein the sensing circuitry is configured to perform the particular logical operation without transferring data via an input/output (I/O) line.

13. The method of claim 11 , wherein the sensing circuitry is configured to perform the particular logical operation without transferring data to a control component external to the array.

14. The method of claim 11 , further comprising retaining the first data value in the dynamic latch unchanged by performing the particular logical operation.

15. The method of claim 11 , further comprising storing the first data value to the sense amplifier from the array of memory cells before loading the first data value to the dynamic latch.

16. The method of claim 11 , wherein performing the particular logical operation includes flipping a latch in the sense amplifier to invert the second data value in the sense amplifier.

17. The method of claim 16 , wherein flipping the latch in the sense amplifier does not change the first data value stored to the dynamic latch.

18. The method of claim 11 , further comprising pre-seeding the sense amplifier with logical operation data.

19. The method of claim 18 , wherein pre-seeding the sense amplifier with logical operation data includes:
forcing the second data value stored to the sense amplifier to a “0” data value when the dynamic latch reflects a “0” data value; and
leaving the second data value stored to the sense amplifier unchanged when the dynamic latch reflects a “1” data value.

20. The method of claim 19 , wherein pre-seeding the sense amplifier with logical operation data includes pre-seeding the sense amplifier with logical operation data prior to storing the result of the particular logical operation in the sense amplifier.

21. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array,
wherein the sensing circuitry comprises:
a sense amplifier directly coupled to a pair of complementary sense lines via a first input node and a second input node; and
a compute component coupled to the sense amplifier and comprising a dynamic latch,
wherein the compute component comprises:
a first source/drain region of a first transistor coupled to a first one of the complementary pair of sense lines and directly coupled to a first source/drain region of a first load transistor;
a first source/drain region of a second transistor coupled to a second one of the complementary pair of sense lines and directly coupled to a first source/drain region of a second load transistor;
a second source/drain region of the first transistor directly coupled to a first source/drain region of a first dynamic latch transistor;
a second source/drain region of the second transistor directly coupled to a first source/drain region of a second dynamic latch transistor;
a second source/drain region of the first dynamic latch transistor directly coupled to the first one of the complementary pair of sense lines;
a second source/drain region of the second dynamic latch transistor directly coupled to the second one of the complementary pair of sense lines;
a gate of the first dynamic latch transistor directly coupled to a second source/drain region of the second load transistor;
a gate of the second dynamic latch transistor directly coupled to a second source/drain region of the first load transistor; and
a gate of the first load transistor directly coupled to a gate of the second load transistor, and

wherein the sensing circuitry is configured to initially store a result of a logical operation in the sense amplifier.

22. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array and comprising:
a sense amplifier coupled to a pair of complementary sense lines; and
a compute component coupled to the sense amplifier, the compute component implementing a dynamic latch,
wherein the compute component comprises:
a first source/drain region of a first transistor directly coupled to a first one of the complementary pair of sense lines and a

Assignees

• Micron Technology Inc

Inventors

• Hush Glen E
• Manning Troy A

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/00 Primary

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title