Method and apparatus for configuring I/O cells of a signal processing IC device into a safe state

Patent metadata

Field	Value
Publication number	US-9785508-B2
Application number	US-201414482387-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Sep 10, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

First claim

The invention claimed is:

1. A peripheral integrated circuit, IC, device for providing support to a data processing IC device, the peripheral IC device comprising:
a fault detection component arranged to detect an occurrence of a fault condition within the data processing IC device; and
a safe state control component arranged to, in response to detection of the fault condition occurring within the data processing IC device by the fault detection component:
cause an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain; and
cause a predefined control signal to be scanned into the scan-chain to configure the I/O cell into a state corresponding to the predefined control signal.

2. The peripheral IC device of claim 1 , wherein the peripheral IC device is arranged to be operably coupled to the data processing IC device via a serial peripheral interface, and the safe state control component is arranged to transmit command signals to the data processing IC device to cause the I/O cell of the data processing IC device to be configured into the scan-chain and to cause the predefined control signal to be scanned into the scan-chain via the serial peripheral interface.

3. The peripheral IC device of claim 1 , wherein the safe state control component is arranged to cause the I/O cell of the data processing IC device to be configured into the scan-chain by sending a command signal to a debug component of the data processing IC device instructing the debug component to configure the I/O cell of the data processing IC device into the scan-chain.

4. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending the command signal to the debug component of the data processing IC device comprising a control signal pattern to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a logical level corresponding to the control signal pattern.

5. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending a command signal to the debug component of the data processing IC device to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a high input impedance.

6. The peripheral IC device of claim 3 , wherein the safe state control component is arranged to cause the predefined control signal to be scanned into the scan-chain by sending a command signal to the debug component of the data processing IC device to cause the debug component to scan in a control signal into the scan-chain to configure the I/O cell to comprise a logical level corresponding to a predefined control signal pattern.

7. The peripheral IC device of claim 3 , wherein the safe state control component is operably coupled to a memory element and arranged to read therefrom a series of command signals for causing the I/O cell of the data processing IC device to be configured into the scan-chain and for causing a predefined control signal to be scanned into the scan-chain to configure the I/O cell into to a state corresponding to the predefined control signal.

8. The peripheral IC device of claim 7 , wherein the safe state control component is further arranged to read from the memory element the control signal to be scanned into the scan-chain.

9. The peripheral IC device of claim 3 , wherein the safe state control component is operably coupled to a fuse element configurable to define the control signal to be scanned into the scan-chain.

10. The peripheral IC device of claim 3 , wherein the control signal to be scanned into the scan-chain is hardcoded into the peripheral IC device.

11. The peripheral IC device of claim 1 , wherein the predefined control signal to be scanned into the scan-chain is arranged to force the I/O cell into to a state comprising at least one of:
a high logical level;
a low logical level; and
a high input impedance level.

12. The peripheral IC device of claim 1 , wherein the fault detection component is arranged to detect the occurrence of at least one of:
an over-current condition within the data processing IC device;
an over-voltage condition within the data processing IC device;
an over-temperature condition within the data processing IC device; and
a watchdog function not being serviced.

13. The peripheral IC device of claim 1 , wherein the fault detection component is arranged to detect the occurrence of fault conditions based on a notification received from the data processing IC device of the detection of a fault condition thereby.

14. The peripheral IC device of claim 1 , wherein the support provided by the peripheral IC device to the data processing IC device comprises at least one from a group comprising:
power regulator functionality;
over current detection functionality;
watchdog functionality; and
physical layer communication functionality.

15. A data processing integrated circuit, IC, device comprising a safety level configuration component, the safety level configuration component being controllable by a peripheral IC device operably coupled to the data processing IC device to:
configure an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain in response to a detection of a fault condition occurring within the data processing IC device; and
cause a predefined control signal to be scanned into the scan-chain to configure the I/O cell into to a state corresponding to the predefined control signal.

16. The data processing IC device of claim 15 , wherein the I/O cell is arranged to be isolated from core functional components of the data processing IC device when configured into the scan-chain by the safety level configuration component.

17. The data processing IC device of claim 15 , wherein the safety level configuration component comprises a debug component of the data processing IC device.

18. The data processing IC device of claim 15 , wherein the scan-chain comprises at least one boundary scan scan-chain.

19. The data processing IC device of claim 15 , wherein the data processing IC device comprises a microprocessor.

20. A method comprising:
detecting, at a detection component, an occurrence of a fault condition within a data processing integrated circuit, IC, device; and
in response to detection of the fault condition occurring within the data processing IC device:
causing, by a safe state control component, an input/output, I/O, cell of the data processing IC device to be configured into a scan-chain; and
causing, by the safe state control component, a predefined control signal to be scanned into the scan-chain to configure the I/O cell into a state corresponding to the predefined control signal.

Assignees

• Moran Robert F
• Devine Alan
• Robertson Alistair Paul
• Nxp Usa Inc

Inventors

• Moran Robert F
• Devine Alan
• Robertson Alistair Paul

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G06F11/0739

  in a data processing system embedded in automotive or aircraft systems · CPC title

• G01R31/3185 Primary

  Reconfiguring for testing, e.g. LSSD, partitioning · CPC title

• G06F2201/805

  Real-time · CPC title