Registering a user-handler in hardware for transactional memory event handling

Patent metadata

Field	Value
Publication number	US-9785462-B2
Application number	US-34651808-A
Country	US
Kind code	B2
Filing date	Dec 30, 2008
Priority date	Dec 30, 2008
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.

First claim

What is claimed is:

1. An apparatus comprising:
a first storage element, which is adapted to be modifiable by non-privileged software to hold a reference to a transactional handler and a plurality of handler events, the first storage element to hold a bit vector with each bit of the bit vector corresponding to one of the plurality of handler events, and wherein each bit corresponding to a handler event is to be set by the non-privileged software to enable an execution circuit to vector execution to the transactional handler in response to an occurrence of the handler event;
a second storage element to hold a status value to indicate the handler event that is to be handled by the transactional handler upon the occurrence of the handler event; and
the execution circuit coupled to the first storage element, the execution circuit to execute a transaction and to vector execution from the transaction to the transactional handler with a skid as low as zero, without software polling, and without intervention from privileged software, based on the reference to the transactional handler to be held in the first storage element in response to the occurrence of the handler event; and
wherein the handler event is selected from a plurality of events consisting of an execution of an instruction that is illegal within a transaction's scope, an access to a non-checkpointed register, an access to a memory type forbidden in the transaction's scope, a system call, and an illegal control transfer.

2. The apparatus of claim 1 , wherein the first storage element includes a register, and wherein the reference to the transactional handler includes a virtual address.

3. The apparatus of claim 2 , wherein the execution circuit vectoring execution from the transaction to the transactional handler comprises the execution circuit performing a jump type of operation with a target address associated with the virtual address and an offset.

4. The apparatus of claim 1 , wherein the non-privileged software includes transactional runtime code.

5. The apparatus of claim 1 , wherein the plurality of events further includes an asynchronous handler event.

6. The apparatus of claim 1 , wherein the plurality of events further includes a synchronous handler event.

7. The apparatus of claim 1 , wherein the plurality of events further consists of a lack of attribute information, a loss of attribute information, a loss of monitored data, and a loss of buffered data.

8. The apparatus of claim 1 , further comprising a third storage element to be readable by the non-privileged software, wherein the third storage element to hold a status value to specify the handler event causing the execution circuit to vector execution to the transactional handler.

9. The apparatus of claim 8 , further comprising a fourth storage element to be updated with a reference to a current instruction pointer before the execution circuit vectors execution from the transaction to the transactional handler.

10. The apparatus of claim 9 , wherein in response to the transactional handler handling the handler event the execution circuit to execute a jump-type instruction using the reference stored in the fourth storage element as the target to return execution to the transaction.

11. A storage device including user-level code, which, when executed, causes a machine to perform the operations of:
registering a transactional handler to associate the transactional handler with a transaction in the user-level code;
associating the transactional handler with a handler event of a plurality of handler events stored in a storage element, the plurality of handler events comprising an execution of an instruction that is illegal within a transaction's scope, an access to a non-checkpointed register, an access to a memory type forbidden in the transaction's scope, a system call, and an illegal control transfer, wherein the storage element is to hold a bit vector with each bit of the bit vector corresponding to one of the plurality of handler events, and wherein a bit corresponding to the handler event is to be set by the user-level code to enable an execution circuit to vector execution to the transactional handler in response to an occurrence of the handler event; and
transferring a control flow to the transactional handler, the transfer to occur with a skid as low as zero, without software polling, and without intervention of privileged level software, in response to the handler event occurring during execution of the transaction based on the transactional handler being associated with the handler event.

12. The storage device of claim 11 , wherein registering the transactional handler includes writing an address of the transactional handler to a register in a processor.

13. The storage device of claim 12 , wherein transferring control flow to the transactional handler without software polling and without intervention of privileged level software comprises performing a first jump-type operation utilizing the address of the transactional handler.

14. The storage device of claim 13 , wherein the user-level code, when executed, further causes the machine to perform the operations of before performing the jump-type operation utilizing the address of the transactional handler updating a return register with a reference to an instruction pointer address at a current point immediately before performing the first jump type operation.

15. The storage device of claim 14 , wherein the user-level code, when executed, further causes the machine to perform the operations of performing a second jump-type operation utilizing the instruction pointer address from the reference to the instruction pointer address held in the return register to return to the current point immediately before the first jump type operation.

16. The storage device of claim 11 , wherein the plurality of events further includes an asynchronous event selected from a group consisting of a lack of attribute information, a loss of attribute information, and a loss of buffered data.

17. The storage device of claim 11 , wherein the plurality of events further includes a synchronous event.

18. The storage device of claim 11 , wherein the privileged level software includes software selected from a group consisting of operating system software, kernel software, and virtual machine monitor (VMM) software.

19. An apparatus comprising:
a handler register to be updated by user-level software, the handler register to hold a reference to a transactional handler;
an event register to be updated by the user-level software to specify a plurality of handler events, wherein the plurality of handler events are each individually selected from a plurality of handler events comprising an execution of an instruction that is illegal within a transaction's scope, an access to a non-checkpointed register, an access to a memory type forbidden in the transaction's scope, a system call, and an illegal control transfer;
a status register to hold a status value to indicate the handler event to be handled by the transactional handler upon an occurrence of one of the plurality of the handler events; and
an execution circuit to vector execution from a transaction to the transactional handler with a skid as low as zero, without software polling, and without intervention of privileged level software, in response to detecting the occurrence of the handler event of the plurality of handler events.

20. The apparatus of claim 19 , wherein the privileged level software intervention includes Oper

Assignees

• Sheaffer Gad
• Raikin Shlomo
• Bassin Vadim
• Intel Corp

Inventors

• Sheaffer Gad
• Raikin Shlomo
• Bassin Vadim

Classifications

• G06F9/528

  by using speculative mechanisms · CPC title

• G06F9/466 Primary

  Transaction processing · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F9/06 Primary

  using stored programs, i.e. using an internal store of processing equipment to receive or retain programs · CPC title