Systems, apparatuses, and methods for data speculation execution

Patent metadata

Field	Value
Publication number	US-9785442-B2
Application number	US-201414582897-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

First claim

We claim:

1. An apparatus comprising:
a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store stride value; and
execution hardware to execute the decoded instruction to:
determine that a restricted transactional memory (RTM) transaction is not occurring,
initiate a data speculation extension (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, wherein in a DSX region stores are buffered and loads are not, and
store the fallback address, wherein the stride value is a number of instructions to have address checks performed on them by the DSX tracking hardware.

2. The apparatus of claim 1 , wherein the portion of the fallback address is a displacement value to be added to an instruction pointer of an instruction immediately following the decoded instruction by the execution hardware.

3. The apparatus of claim 1 , wherein the portion of the fallback address is a complete address.

4. The apparatus of claim 1 , wherein the operand to store a portion of the fallback address is an immediate value.

5. The apparatus of claim 1 , wherein the operand to store a portion of the fallback address is a register.

6. The apparatus of claim 1 , further comprising:
a DSX nesting counter to store a value corresponding to a number of DSX region starts with no corresponding DSX region ends.

7. A method comprising:
decoding an instruction using a hardware decoder, the instruction to include an opcode and an operand to store a portion of a fallback address and operand to store a stride value; and
executing decoded instruction to:
determine that a restricted transactional memory (RTM) transaction is not occurring,
initiate a data speculation extension (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, wherein in a DSX region stores are buffered and loads are not, and
store the fallback address, wherein the stride value is a number of instructions to have address checks performed on them by the DSX tracking hardware.

8. The method of claim 7 , wherein the portion of the fallback address is a displacement value to be added to an instruction pointer of an instruction immediately following the decoded instruction by the execution hardware.

9. The method of claim 7 , wherein the portion of the fallback address is a complete address.

10. The method of claim 7 , wherein the operand to store a portion of the fallback address is an immediate value.

11. The method of claim 7 , wherein the operand to store a portion of the fallback address is a register.

12. The method of claim 7 , wherein the executing further comprise:
determining that an restricted transactional memory (RTM) transaction is occurring and process the RTM transaction.

13. The method of claim 7 , further comprising:
storing a value corresponding to a number of DSX region starts with no corresponding DSX region ends.

14. A non-transitory machine readable medium storing instructions which when executed by a machine cause circuitry to be fabricated, the circuitry comprising:
a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value; and
execution hardware to execute the decoded instruction to:
determine that a restricted transactional memory (RTM) transaction is not occurring,
initiate a data speculation extension (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, wherein in a DSX region stores are buffered and loads are not, and
store the fallback address, wherein the stride value is a number of instructions to have address checks performed on them by the DSX tracking hardware.

15. The non-transitory machine readable medium of claim 14 , wherein the portion of the fallback address is a displacement value to be added to an instruction pointer of an instruction immediately following the decoded instruction by the execution hardware.

16. The non-transitory machine readable medium of claim 14 , wherein the portion of the fallback address is a complete address.

17. The non-transitory machine readable medium of claim 14 , wherein the operand to store a portion of the fallback address is an immediate value.

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Hughes Christopher J
• Valentine Robert
• Girkar Milind B
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Hughes Christopher J
• Valentine Robert
• Girkar Milind B

Classifications

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title