Photonic integrated circuit (PIC) and silicon photonics (SIP) circuitry device

Patent metadata

Field	Value
Publication number	US-9784933-B2
Application number	US-201514689571-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Dec 18, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A device may include a first substrate. The device may include an optical source. The optical source may generate light when a voltage or current is applied to the optical source. The optical source may be being provided on a first region of the first substrate. The device may include a second substrate. A second region of the second substrate may form a cavity with the first region of the first substrate. The optical source may extend into the cavity. The device may include an optical interconnect. The optical interconnect may be provided on or in the second substrate and outside the cavity. The optical interconnect may be configured to receive the light from the optical source.

First claim

What is claimed is:

1. A device, comprising:
a first substrate;
an optical source, the optical source generating light when a voltage or current is applied to the optical source, the optical source being provided on a first region of the first substrate;
a second substrate,
a second region of the second substrate forming a cavity with the first region of the first substrate, the optical source extending into the cavity, the first substrate being provided on the second substrate;
a surface connector provided on a surface of the second substrate;
an electrical connector provided on a surface of the first substrate;
wherein the second substrate includes a conductive pass through that electrically connects the surface connector with the electrical connector, the conductive pass through extending beneath a portion of the first substrate and being spaced from the surface of the second substrate; and
an optical interconnect, the optical interconnect being provided on or in the second substrate and outside the cavity, the optical interconnect being configured to receive the light from the optical source.

2. The device of claim 1 , where the cavity is formed from the second substrate based on at least one of:
selectively etching the second substrate,
selectively stamping the second substrate,
selectively ablating material from the second substrate, or
selectively depositing material onto the second substrate.

3. The device of claim 1 , where the cavity is an environmentally sealed cavity.

4. The device of claim 1 , where at least one of the first substrate or the second substrate is comprised of at least one of:
a silicon semiconductor based material,
an indium-phosphide based material,
a gallium arsenide based material,
a fiber reinforced polymer composite based material,
a polyimide based material,
a liquid crystal polymer based material,
a silicon dioxide based material,
a silicon nitride based material,
an aluminum nitride based material,
a beryllium oxide based material, or
an aluminum oxide based material.

5. The device of claim 1 , where the optical source is a laser.

6. The device of claim 1 , further comprising:
a silicon photonics circuit provided on a third region of the second substrate, the silicon photonics circuit being optically coupled to the optical source by the optical interconnect.

7. The device of claim 1 , further comprising:
a photonic integrated circuit (PIC) provided on the first region of the first substrate, the PIC including the optical source.

8. The device of claim 7 , where the PIC is provided on the first region of the first substrate via at least one of:
flip-chip bonding, or
direct bonding.

9. The device of claim 7 , further comprising:
another PIC provided on a third region of a third substrate, the third substrate being attached to the second substrate.

10. The device of claim 1 , where the second region of the second substrate includes a particular material that forms a portion of a hermetic seal for the cavity,
the particular material including at least one of:
an epitaxial material,
an amorphous semiconductor material,
an amorphous ceramic material, or
a metal material.

11. The device of claim 1 , where the second substrate is comprised of multiple layers of material, the multiple layers of material being selectively patterned to form an electrical interconnect.

12. The device of claim 11 , where the multiple layers of material includes at least one of:
a selectively etched layer,
a selectively stamped layer,
a selectively ablated layer, or
a selectively deposited layer.

13. The device of claim 11 , where the second substrate includes an electrical device or an optical device integrated into the multiple layers of material.

14. The device of claim 1 , where the optical interconnect includes at least one of:
an optical butt coupling,
a waveguide coupling,
a free space coupling,
an optical lens, or
an optical wire bond coupling.

15. A device, comprising:
a first substrate, the first substrate including one or more waveguides for coupling a first set of optical devices to a second set of optical devices;
a second substrate, the second substrate being configured to attach to the first substrate and form an environmentally sealed cavity between the first substrate and the second substrate, the second substrate being configured to mount the first set of optical devices;
a surface connector provided on a surface of the second substrate;
an electrical connector provided on a surface of the first substrate;
wherein the second substrate includes a conductive pass through that electrically connects the surface connector with the electrical connector, the conductive pass through extending beneath a portion of the first substrate and being spaced from the surface of the second substrate; and
a third substrate, the third substrate being configured to attach to the first substrate, the third substrate being configured to mount the second set of optical devices.

16. The device of claim 15 , where the first substrate is further configured to:
facilitate alignment of an output of the first set of optical devices with an input of the second set of optical devices to a tolerance of less than approximately 5 microns.

17. The device of claim 15 , where the first set of optical devices are mounted on the second substrate at a location within the environmentally sealed cavity.

18. The device of claim 15 , where the environmentally sealed cavity is a hermetically sealed cavity.

19. The device of claim 15 , where the one or more waveguides include at least one of:
an inorganic thin film material, or
an organic thin film material.

20. The device of claim 19 , where the inorganic thin film material includes at least one of:
an amorphous-silicon based material,
a silicon nitride based material,
a silicon oxide based material,
an indium phosphide based material, or
a gallium arsenide based material.

21. The device of claim 19 , where the organic thin film material includes at least one of:
an epoxy based material,
a fiber reinforced epoxy based material,
an organic silicon based material,
a liquid crystal polymer based material,
a photo-definable polymer based material,
a benzocyclobutene based material, or
a polyimide based material.

22. The device of claim 15 , where the first substrate is an insulator-based substrate comprised of multiple layers of material,
one or more of the multiple layers of material being electrically insulating material,
one or more of the multiple layers of material being electrically conductive material,
the multiple layers of material being patterned to form one or more electrical interconnections.

23. The device of claim 15 , where the first substrate further comprises:
a particular waveguide configured to receive optical signal gain for an optical signal associated with the first set of optical devices.

24. The device of claim 15 , further comprising:
a set of waveguides attached to the first substrate,
the set of waveguides being configured to receive or provide an optical signal to or from another device.

25. A device, comprising:
a first substrate including a cavity in a surface of the first substrate,
the surface of the first substrate being configured to receive a photonic integrated circuit (PIC) provided on a second substrate, the surface of the f

Assignees

• Infinera Corp

Inventors

• Osenbach John W
• Butrie Timothy
• Kish Jr Fred A
• Reffle Michael

Classifications

• G02B6/4273

  with heat insulation means to thermally decouple or restrain the heat from spreading · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• G02B6/4215

  the intermediate optical elements being wavelength selective optical elements, e.g. variable wavelength optical modules or wavelength lockers (G02B6/4246 takes precedence) · CPC title

• G02B2006/12061

  Silicon · CPC title

• G02B6/423

  using guiding surfaces for the alignment · CPC title