Long-term packaging for the protection of implant electronics

US9781842B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9781842-B2
Application numberUS-201314142180-A
CountryUS
Kind codeB2
Filing dateDec 27, 2013
Priority dateAug 5, 2013
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.

First claim

Opening claim text (preview).

What is claimed is: 1. A micropackaged device, said micropackaged device comprising: a device; a thin-film substrate for securing said device, said thin-film substrate comprising: a first thin-film parylene layer, which is 1-10 μm thick; a metal adjacent to the first thin-film parylene layer; a second thin-film parylene layer, which is 20-60 μm thick, and which is adjacent to the metal to form a thin-film metal thin-film sandwich, wherein said second layer of thin-film has an opening, said opening having at least one electrical contact provided on an internal surface thereof, said opening configured to accept at least one electrical circuit device and to provide electrical communication between said at least one electrical contact and said at least one electrical circuit device; a corrosion barrier affixed to said substrate with an adhesive, wherein the corrosion barrier is made of a metal, ceramic or glass, which is disposed above and below the device; at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer made of parylene, silicone or a combination thereof configured to encapsulate said micropackaged device, wherein said encapsulation material layer creates an enclosed housing, wherein the corrosion barrier is 30% to 99% of the total area of the interior of enclosed housing, hermetically sealing said substrate and said corrosion barrier. 2. The micropackaged device of claim 1 , wherein said device is a member selected from the group consisting of an integrated circuit (IC) chip, a printed circuit board (PCB), a microelectromechanical system (MEMS), a capacitor, an inductor, an oscillator, and a combination thereof. 3. The micropackaged device of claim 1 , wherein said corrosion barrier is a material selected from the group consisting of metal and ceramic. 4. The micropackaged device of claim 3 , wherein said corrosion barrier is made from a metal. 5. The micropackaged device of claim 4 , wherein said metal is a metal film. 6. The micropackaged device of claim 1 , wherein said corrosion barrier is made from glass. 7. The micropackaged device of claim 1 , wherein said adhesive is a low permeation adhesive. 8. The micropackaged device of claim 1 , wherein said adhesive is a member selected from the group consisting of an epoxy, silicone and polyimide. 9. The micropackaged device of claim 1 , wherein said encapsulation material layer is parylene. 10. The micropackaged device of claim 1 , wherein said encapsulation material layer is silicone. 11. The micropackaged device of claim 1 , wherein said encapsulation material layer comprises a plurality of encapsulation material layers. 12. The micropackaged device of claim 1 , wherein the corrosion barrier is coextensive with about 30% to about 60% of the total area of the interior of enclosed housing. 13. The micropackaged device of claim 1 , wherein said micropackaged device is an epiretinal implant integrated device. 14. The micropackaged device of claim 1 , wherein the thin-film substrate extends from the enclosed housing to an outer surface. 15. The micropackaged device of claim 14 , wherein the outer surface comprises an electrode array in electrical communication with the substrate. 16. The micropackaged device of claim 14 , wherein the outer surface extends from the enclosed housing through the feedthrough. 17. The micropackaged device of claim 14 , wherein the substrate extension to the outer surface is a made from a material selected from the group consisting of parylene, silicone, or a metal alloy. 18. The micropackaged device of claim 1 , wherein the device having at least one electrical circuit is an integrated circuit (IC) chip. 19. The micropackaged device of claim 18 , wherein the device is integrated in the substrate by a conductive epoxy squeegee electrical connection. 20. The micropackaged device of claim 18 , wherein the device is integrated into the substrate by a photo-patternable adhesive used as a mechanical glue. 21. The micropackaged device of claim 20 , wherein the photo-patternable adhesive or epoxy is photoresist. 22. The micropackaged device of claim 21 , wherein the photoresist is a member selected from the group consisting of SU-8, AZ4620, AZ1518, AZ4400, AZ9260, THB-126N, WPR-5100, BCB, and polyimide. 23. The micropackaged device of claim 1 , wherein the substrate is first treated with oxygen plasma to enhance bonding.

Assignees

Inventors

Classifications

  • Chemical vapour deposition · CPC title

  • Encapsulation comprising more than one layer · CPC title

  • Moulded encapsulation of mounted components · CPC title

  • Photodevelopable thick film, e.g. conductive or insulating paste · CPC title

  • Blade or squeegee, e.g. for screen printing or filling of holes · CPC title

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Frequently asked questions

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What does patent US9781842B2 cover?
The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.
Who is the assignee on this patent?
California Inst Of Techn
What technology area does this patent fall under?
Primary CPC classification H05K3/284. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).