Simultaneous and selective wide gap partitioning of via structures using plating resist

Patent metadata

Field	Value
Publication number	US-9781830-B2
Application number	US-201414205337-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 4, 2005
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

First claim

The invention claimed is:

1. A multilayer printed circuit board, comprising:
a first dielectric layer;
a first plating resist selectively positioned in the first dielectric layer;
a second plating resist selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist; and
a through hole extending through the first dielectric layer, the first plating resist, and the second plating resist, where an interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist to form a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

2. The multilayer printed circuit board of claim 1 , wherein the first plating resist is located adjacent a first surface of a first core or sub-composite structure, and the second plating resist is located adjacent a second surface of a second core or sub-composite structure.

3. The multilayer printed circuit board of claim 1 , wherein the first plating resist is located adjacent a first surface of a first core or sub-composite structure and the second plating resist is located adjacent an opposite second surface of the first core or sub-composite structure.

4. The multilayer printed circuit board of claim 1 , wherein at least one of the first plating resist and second plating resist is located within a first core structure or sub-composite structure, where the first dielectric layer and second dielectric layer are part of the first core structure or sub-composite structure.

5. The multilayer printed circuit board of claim 1 , wherein both the first plating resist and second plating resist are located within a first core structure or sub-composite structure, where the first dielectric layer and second first dielectric layer are part of the first core structure or sub-composite structure.

6. The multilayer printed circuit board of claim 1 , wherein the first plating resist is located within a first core structure or sub-composite structure, and the second plating resist is located within a second core structure or sub-composite structure, where the first dielectric layer is part of the first core structure or sub-composite structure and the second dielectric layer is part of the second core structure or sub-composite structure.

7. The multilayer printed circuit board of claim 1 , wherein the first plating resist and second plating resist are located within the first dielectric layer, and further comprising:
a third plating resist selectively positioned in the second dielectric layer; and
a fourth plating resist selectively positioned in the second dielectric layer, the third plating resist separate from the fourth plating resist, wherein the through hole extends through the second dielectric layer, the third plating resist, and the fourth plating resist, where the interior surface of the through hole is plated with the conductive material except along a second length between the third plating resist and the fourth plating resist to form a third via segment electrically isolated from the first via segment and second via segment.

8. The multilayer printed circuit board of claim 1 , further comprising:
one or more core structures or sub-composite structures; and
one or more additional dielectric layers in between the one or more core structures or sub-composite structures.

9. The multilayer printed circuit board of claim 1 , wherein a first thickness of the first plating resist is less than a second thickness of the first dielectric layer.

10. The multilayer printed circuit board of claim 1 , wherein a first thickness of the first plating resist is approximately the same as a second thickness of the first dielectric layer.

11. The multilayer printed circuit board of claim 1 , wherein the first plating resist comprises an insulating hydrophobic resinous material resistant to deposition of a catalytic species capable of catalyzing an electroless metal deposition.

12. The multilayer printed circuit board of claim 1 , wherein at least one of the first plating resist and second plating resist has a radius greater than a radius of the through hole.

13. The multilayer printed circuit board of claim 1 , wherein the first via segment and second via segment are separated along a circumference of the partitioned plated through hole.

Assignees

• Sanmina Corp

Inventors

• Iketani Shinichi
• Kersten Dale
• Dudnikov Jr George

Classifications

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/036

  Multilayers with layers of different types · CPC title

• H05K2203/0713

  Plating poison, e.g. for selective plating or for preventing plating on resist · CPC title