Transformer comprising a rounded coil

Patent metadata

Field	Value
Publication number	US-9780161-B2
Application number	US-201514837880-A
Country	US
Kind code	B2
Filing date	Aug 27, 2015
Priority date	Apr 20, 2012
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

First claim

What is claimed is:

1. A transformer formed over a semiconductor substrate, the transformer comprising:
an isolation layer disposed on the semiconductor substrate, wherein the isolation layer comprises a homogeneous continuous dielectric material extending between a top surface of the isolation layer and a bottom surface of the isolation layer, and wherein the top surface of the isolation layer is planar;
a first coil disposed in a bottom half of the isolation layer; and
a second coil disposed above the first coil in a top half of the isolation layer that is galvanically isolated from the bottom half of the isolation layer, wherein the transformer is a coreless transformer, wherein the isolation layer, the first coil, and the second coil are part of the coreless transformer, and wherein the second coil comprises
an upper section comprising first sidewalls that are vertical and straight along a vertical cross section, and
a lower section comprising second sidewalls that are curved and concave along the vertical cross section, wherein the lower section comprises an upper region comprising a first radius of curvature and a lower region comprising a second radius of curvature that is the maximum radius of curvature of the lower region, wherein the first radius of curvature is larger than the second radius of curvature.

2. The transformer according to claim 1 , further comprising a barrier layer disposed between the second coil and the isolation layer, wherein the barrier layer directly contacts the second sidewalls of the second coil.

3. The transformer according to claim 1 , further comprising an integrated circuit disposed in the semiconductor substrate.

4. The transformer according to claim 1 , wherein the first coil is substantially aligned with the second coil.

5. The transformer according to claim 4 , wherein at least one of the first coil and the second coil comprise copper or aluminum.

6. The transformer of claim 1 , wherein the first coil comprises aluminum, and wherein the second coil comprises copper.

7. The transformer of claim 1 , wherein the second sidewalls have a radius of curvature that is the same for at least about 180 degrees.

8. The transformer of claim 1 , wherein the second sidewalls have a radius of curvature of the lower region that is the same for at least one of a lower region for at least about 90 degrees and that is different than a radius of curvature of the upper region.

9. A semiconductor structure comprising:
a first coil supported by a substrate;
a dielectric layer disposed over the substrate and the first coil;
an opening in the dielectric layer comprising a concave surface, the opening comprising a first width at a top surface of the dielectric layer and a second width at a central region of the opening, wherein the first width is smaller than the second width; and
a spacer disposed over the top surface of the dielectric layer and extending vertically towards the substrate through the opening, wherein the spacer comprises a first vertical major surface that is facing the opening and a second vertical major surface that is facing the dielectric layer, and wherein the first vertical major surface and the second vertical major surface are exposed up to the top surface of the dielectric layer.

10. The semiconductor structure of claim 9 , wherein the dielectric layer is a single dielectric layer.

11. The semiconductor structure of claim 9 , wherein the spacer comprises polycrystalline silicon.

12. The semiconductor structure of claim 9 , wherein the spacer comprises silicon oxide.

13. The semiconductor structure of claim 9 , wherein the spacer comprises silicon nitride.

14. The semiconductor structure of claim 9 , wherein the spacer comprises photoresist.

15. The semiconductor structure of claim 9 , wherein the spacer comprises a metal.

16. The semiconductor structure of claim 9 , wherein the concave surface comprises a lower region having a first radius of curvature and an upper region having a second radius of curvature, the first radius of curvature being larger than the second radius of curvature.

17. A coreless transformer comprising:
a semiconductor substrate;
a patterned isolation region disposed over the semiconductor substrate, wherein the patterned isolation region comprises a homogeneous continuous dielectric material extending between a top surface of the patterned isolation region and a bottom surface of the patterned isolation region, and wherein a top surface of the patterned isolation region is planar;
a first primary coil and a second primary coil disposed completely within a top half of the patterned isolation region; and
a first secondary coil and a second secondary coil disposed within a bottom half of the patterned isolation region, wherein the first primary coil is electromagnetically coupled with the first secondary coil, wherein the second primary coil is electromagnetically coupled with the second secondary coil, wherein the patterned isolation region, the first primary coil, the second primary coil, the first secondary coil, and the second secondary coil are part of the coreless transformer, and wherein the first primary coil and the second primary coil each comprise
an upper section comprising first sidewalls that are vertical and straight along a vertical cross section, and
a lower section comprising second sidewalls that are curved and concave along the vertical cross section, the lower section comprising an upper region and a lower region, wherein the upper region comprises a continuously changing first radius of curvature, wherein the lower region comprises a continuously changing second radius of curvature, wherein an average rate of change of the continuously changing first radius of curvature is smaller than an average rate of change of the continuously changing second radius of curvature, and wherein the first primary coil and the second primary coil are circular in shape in a top view.

18. The coreless transformer of claim 17 , wherein a top width of the first primary coil and the second primary coil along the vertical cross section is smaller than a central width of the first primary coil and the second primary coil along the vertical cross section.

19. A coreless transformer formed over a semiconductor substrate, the coreless transformer comprising:
an isolation layer disposed on the semiconductor substrate, wherein the isolation layer comprises a homogeneous continuous dielectric material extending between a top surface of the isolation layer and a bottom surface of the isolation layer, and wherein a top surface of the isolation layer is planar;
a first coil disposed under the isolation layer within the semiconductor substrate; and
a second coil disposed above the first coil and completely in a top half of the isolation layer, wherein the top half of the isolation layer is galvanically isolated from a top surface of the semiconductor substrate comprising the first coil, wherein the isolation layer, the first coil, and the second coil are part of the coreless transformer, and wherein the second coil comprises
an upper section comprising first sidewalls that are vertical and straight along a vertical cross section, and
a lower section comprising second sidewalls that are curved and concave along the vertical cross section, wherein the second sidewalls comprise a point, an upper region having a first volume above the point, and a lower region having a second volume below the point, wherein a tangent line drawn at the point is vertical, and wherein the first volum

Assignees

• Infineon Technologies Ag

Inventors

• Menath Markus
• Fischer Thomas
• Wendt Hermann

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5366

  the bond wires having kinks · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title