Semiconductor memory device including a plurality of columnar structures and a plurality of electrode films

US9780105B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9780105-B2
Application numberUS-201615200254-A
CountryUS
Kind codeB2
Filing dateJul 1, 2016
Priority dateDec 30, 2015
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor memory device according to one embodiment, includes a stacked body including a plurality of electrode films stacked separated from each other along a first direction, a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor layer, a charge storage film provided between one of the columnar structures and the electrode films, and an insulating film dividing one of the electrode films disposed in an upper portion of the stacked body and not dividing other one of the electrode films disposed in a lower portion of the stacked body. A shortest distance between the columnar structures disposed on one side of the insulating film being shorter than a shortest distance between the columnar structures disposed with the insulating film interposed between the columnar structures.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor memory device, comprising: a stacked body including a plurality of electrode films stacked along a first direction and separated from each other; a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor layer; a charge storage portion provided between one of the columnar structures and one of the electrode films; and an insulating film dividing one of the electrode films disposed in an upper portion of the stacked body and not dividing other one of the electrode films disposed in a lower portion of the stacked body, wherein a shortest distance between the columnar structures disposed on one side of the insulating film being shorter than a shortest distance between the columnar structures disposed with the insulating film interposed between the columnar structures, the insulating film extends in a second direction crossing the first direction, as viewed from the first direction, the plurality of columnar structures is not disposed at first lattice points and is disposed at second lattice points except for the first lattice points, among lattice points of a lattice, the first lattice points being located in the insulating film and being arranged in a row along the second direction, the lattice being configured of a plurality of first imaginary straight lines and a plurality of second imaginary straight lines, the plurality of first imaginary straight lines extending in a third direction crossing the first direction and arranged at equal intervals, and the plurality of second imaginary straight lines extending in a fourth direction crossing the third direction and arranged at equal intervals. 2. The semiconductor memory device according to claim 1 , further comprising insulating members disposed on both sides of the stacked body in a fifth direction, the fifth direction crossing the first direction and the second direction. 3. The semiconductor memory device according to claim 2 , further comprising: a semiconductor substrate on which the stacked body is disposed; and a conductive member provided in the insulating member and extending in the first direction, a lower end of the conductive member being connected to the semiconductor substrate. 4. The semiconductor memory device according to claim 1 , wherein the plurality of columnar structures is arranged along a plurality of rows extending in the second direction. 5. The semiconductor memory device according to claim 4 , wherein the columnar structures are periodically arranged along the second direction in each of the rows. 6. The semiconductor memory device according to claim 5 , wherein positions of the columnar structures in the second direction are shifted from each other in the rows adjacent to each other. 7. The semiconductor memory device according to claim 1 , wherein the one of the electrode films disposed in the upper portion of the stacked body is thicker than the other one of the electrode films disposed in the lower portion of the stacked body. 8. The semiconductor memory device according to claim 1 , wherein the charge storage portion is insulating. 9. The semiconductor memory device according to claim 1 , wherein the charge storage portion is conductive. 10. The semiconductor memory device according to claim 1 , further comprising: a tunnel insulating film disposed between the columnar structure and the charge storage portion; and a block insulating film disposed between the charge storage portion and the electrode films. 11. The semiconductor memory device according to claim 1 , wherein an area, in the electrode films where the columnar structure is disposed that has not the columnar structure directly below the insulating film in the stacked body. 12. A semiconductor memory device comprising: a plurality of electrode films stacked along a first direction and separated from each other; a plurality of columnar structures extending in the first direction and piercing the plurality of electrode films; and a charge storage portion provided between one of the plurality of columnar structures and one of the plurality of electrode films, wherein the plurality of columnar structures being not disposed at first lattice points arranged in a particular one row that exists periodically along a second direction and being disposed at second lattice points except for the first lattice points, as viewed from the first direction among lattice points of a lattice, the first lattice points being disposed on the electrode films, and the lattice being configured of a plurality of imaginary straight lines extending in a third direction and arranged at equal intervals and a plurality of imaginary straight lines extending in a fourth direction crossing the third direction and arranged at equal intervals. 13. The semiconductor memory device according to claim 12 , further comprising insulating members disposed on both sides of the stacked body in a fifth direction, the third direction crossing the first direction and the second direction. 14. The semiconductor memory device according to claim 13 , further comprising: a semiconductor substrate on which the stacked body is disposed; and a conductive member provided in the insulating member and extending in the first direction, a lower end of the conductive member being connected to the semiconductor substrate. 15. The semiconductor memory device according to claim 12 , wherein the plurality of columnar structures is arranged along a plurality of rows extending in the second direction. 16. The semiconductor memory device according to claim 15 , wherein the columnar structures are periodically arranged along the second direction in each of the rows. 17. The semiconductor memory device according to claim 16 , wherein positions of the columnar structures in the second direction are shifted from each other in the rows adjacent to each other.

Assignees

Inventors

Classifications

  • H10P50/73Primary

    using masks for insulating materials · CPC title

  • using masks for conductive or resistive materials · CPC title

  • Layouts of interconnections · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9780105B2 cover?
A semiconductor memory device according to one embodiment, includes a stacked body including a plurality of electrode films stacked separated from each other along a first direction, a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor layer, a charge storage film provided between one of the columnar structures and the ele…
Who is the assignee on this patent?
Toshiba Memory Corp
What technology area does this patent fall under?
Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).