Dual-port SRAM devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9780097-B2
Application number	US-201514965316-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Dec 30, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.

First claim

What is claimed is:

1. A dual-port SRAM device, comprising:
a substrate including,
a field region,
an isolation layer pattern on the field region, and
first to fourth active fins protruding from the isolation layer pattern and extending in a first direction; and

a unit cell including,
first and second gate structures on the first, second and fourth active fins, each of the first and second gate structures extending in a second direction crossing the first direction,
third and fourth gate structures on the first, second and third active fins, each of the third and fourth gate structures extending in the second direction,
fifth and sixth gate structures on the third active fin, each of the fifth and sixth gate structures extending in the second direction,
a first contact plug electrically connecting the sixth gate structure and the third gate structure,
seventh and eighth gate structures on the fourth active fin, each of the seventh and eighth gate structures extending in the second direction, and
a second contact plug electrically connecting the seventh gate structure and the second gate structure.

2. The dual-port SRAM device of claim 1 , wherein
the third gate structure on the first active fin and the second gate structure on the second active fin form first and second pull-up transistors, respectively, and
the third and sixth gate structures electrically connected to each other through the first contact plug on the third active fin, and the second and seventh gate structures electrically connected to each other through the second contact plug on the fourth active fin form first and second pull-down transistors, respectively.

3. The dual-port SRAM device of claim 2 , wherein
the fifth gate structure on the third active fin and the first gate structure on the fourth active fin form first and second pass-gate transistors, respectively, and
the fourth gate structure on the third active fin and the eighth gate structure on the fourth active fin form third and fourth pass-gate transistors, respectively.

4. The dual-port SRAM device of claim 3 , further comprising:
a first word line electrically connected to the fifth and first gate structures forming the first and second pass-gate transistors, respectively; and
a second word line electrically connected to the fourth and eighth gate structures forming the third and fourth pass-gate transistors, respectively.

5. The dual-port SRAM device of claim 3 , further comprising:
a third contact plug electrically connecting a first pass-gate source/drain region of the first pass-gate transistor and a first pull-up source/drain region of the first pull-up transistor, and
a fourth contact plug electrically connecting a fourth pass-gate source/drain region of the fourth pass-gate transistor and a second pull-up source/drain region of the second pull-up transistor.

6. The dual-port SRAM device of claim 5 , wherein each of the third and fourth contact plugs includes a first portion extending in the first direction and a second portion extending in the second direction.

7. The dual-port SRAM device of claim 5 , wherein the third and fourth contact plugs are in point symmetry with respect to a center of the unit cell.

8. The dual-port SRAM device of claim 5 , wherein
the third pass-gate transistor includes a third pass-gate source/drain region electrically connected to the third contact plug through a fifth contact plug, first and second vias, and a first connection line, and
the second pass-gate transistor includes a second pass-gate source/drain region electrically connected to the fourth contact plug through a sixth contact plug, third and fourth vias, and a second connection line.

9. The dual-port SRAM device of claim 8 , wherein
the third and fifth contact plugs have top surfaces coplanar with each other, the first and second vias contact the top surfaces of the third and fifth contact plugs, respectively, and the first connection line contacts top surfaces of the first and second vias, and
the fourth and sixth contact plugs have top surfaces coplanar with each other, the third and fourth vias contact the top surfaces of the fourth and sixth contact plugs, respectively, and the second connection line contacts top surfaces of the third and fourth vias.

10. The dual-port SRAM device of claim 9 , wherein each of the first and second connection lines extends in the first direction.

11. The dual-port SRAM device of claim 9 , further comprising:
a power line extending in the first direction, the power line being electrically connected to the first pull-up source/drain region through a seventh contact plug and a fifth via, and being electrically connected to the second pull-up source/drain region through an eighth contact plug and a sixth via; and
a ground line extending in the first direction, the ground line being electrically connected to the first pull-down source/drain region through a ninth contact plug and a seventh via, and being electrically connected to the second pull-down source/drain region through a tenth contact plug and an eighth via.

12. The dual-port SRAM device of claim 11 , further comprising:
a first bit line extending in the first direction, the first bit line being electrically connected to the first pass-gate source/drain region;
a first complementary bit line extending in the first direction, the first complementary bit line being electrically connected to the second pass-gate source/drain region;
a second bit line extending in the first direction, the second bit line being electrically connected to the third pass-gate source/drain region; and
a second complementary bit line extending in the first direction, the second complementary bit line being electrically connected to the fourth pass-gate source/drain region.

13. The dual-port SRAM device of claim 12 , wherein the first and second connection lines, the power line, the ground line, the first and second bit lines, and the first and second complementary bit lines have a top surface at a same level.

14. The dual-port SRAM device of claim 1 , wherein
the first and second active fins are in point symmetry with respect to a center of the unit cell, and
the third and fourth active fins are in point symmetry with respect to a center of the unit cell.

15. The dual-port SRAM device of claim 1 , wherein
the first and second gate structures and the third and fourth gate structures are in point symmetry with respect to a center of the unit cell, and
the fifth and sixth gate structures and the seventh and eighth gate structures are in point symmetry with respect to a center of the unit cell.

16. The dual-port SRAM device of claim 1 , wherein
the first, second, third and fourth active fins are the only active fins included in the unit cell, and
the first and second gate structures are only on the first, second and fourth active fins.

17. The dual-port SRAM device of claim 1 , wherein
the first, second, third and fourth active fins are the only active fins included in the unit cell, and
the third and fourth gate structures are only on the first, second and third active fins.

18. The dual-port SRAM device of claim 1 , wherein
the first, second, third and fourth active fins are the only active fins included in the unit cell, and
the fifth and sixth gate structures are only on the third active fm.

19. The dual-port SRAM device of claim 1 , wherein
the first, second, third and fourth active fins are the only active fins included in the unit cell, and
the seventh and eighth gate struct

Assignees

• Lee Kyo-Wook
• Lee Dong-Hun
• Hong Hee-Bum
• Cho Yong-Rae
• Samsung Electronics Co Ltd

Inventors

• Lee Kyo-Wook
• Lee Dong-Hun
• Hong Hee-Bum
• Cho Yong-Rae

Classifications

• H01L29/7851

  Electricity · mapped topic

• H01L27/1104 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H10D84/853

  comprising FinFETs · CPC title