Stacked semiconductor package including reconfigurable package units

Patent metadata

Field	Value
Publication number	US-9780071-B2
Application number	US-201514884916-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Jul 14, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer. The semiconductor package may include coupling members interposed between the first bonding pads of the first semiconductor chip and the through vias of the reconfigurable package unit and between the respective through vias of the stacked reconfigurable package units.

First claim

The invention claimed is:

1. A semiconductor package, comprising:
a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface;
one or more reconfigurable package units stacked over the first semiconductor chip, each comprising:
a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch different from the first pitch on a second active surface;
a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch;
a molding layer surrounding at least side surfaces of the second semiconductor chip and the semiconductor chip connector; and
redistribution lines, extending from second bonding pads over the molding layer to coupling pads, formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer so as to electrically couple the second bonding pads and the through vias; and

coupling members interposed between the first bonding pads of the first semiconductor chip and the through vias of the reconfigurable package unit and between the respective through vias of the stacked reconfigurable package units.

2. The semiconductor package of claim 1 , wherein the first semiconductor chip comprises a SoC (System on Chip), and the second semiconductor chip comprises a memory chip.

3. The semiconductor package of claim 1 , wherein the first semiconductor chip and the reconfigurable package unit have a similar cross-sectional size to each other.

4. The semiconductor package of claim 1 , wherein the first bonding pads of the first semiconductor chip are arranged on the first active surface under the through vias of the semiconductor chip connector.

5. The semiconductor package of claim 1 , wherein the second bonding pads of the second semiconductor chip are arranged at an edge of the second active surface adjacent to the semiconductor chip connector.

6. The semiconductor package of claim 1 , wherein the semiconductor chip connector has a first surface, a second surface facing the first surface, the coupling pads arranged on the first surface and coupled to the redistribution lines, and internal lines formed therein so as to couple the coupling pads and the through vias, respectively.

7. The semiconductor package of claim 6 , wherein the coupling pads are arranged at an edge of the first surface of the semiconductor chip connector, the edge being adjacent to the second semiconductor chip, and the through vias are arranged at an edge facing the edge at which the coupling pads are arranged.

8. The semiconductor package of claim 6 , wherein the first bonding pads, the second bonding pads, the coupling pads, and the through vias are arranged in two lines, respectively, and the internal lines are formed in multiple stages in the semiconductor chip connector.

9. The semiconductor package of claim 1 , wherein the molding layer is formed of an insulating material.

10. The semiconductor package of claim 1 , wherein the molding layer is formed to expose the second surfaces of the second semiconductor chip and the semiconductor chip connector.

11. The semiconductor package of claim 1 , wherein the coupling members comprise conductive bumps.

12. The semiconductor package of claim 1 , further comprising a substrate arranged on a first bottom surface of the first semiconductor chip, having a top surface facing the first bottom surface of the first semiconductor chip and a bottom surface facing the top surface, and electrically coupled to the first semiconductor chip.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang Eun
• Ko Eun
• Park Yong Jae

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title