Semiconductor package

Patent metadata

Field	Value
Publication number	US-9780047-B1
Application number	US-201615358527-A
Country	US
Kind code	B1
Filing date	Nov 22, 2016
Priority date	Apr 4, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A semiconductor package includes: a first substrate including a first ground conductor disposed on at least a second surface of a first surface and the second surface; a plurality of electronic elements mounted on the first surface and the second surface of the first substrate; a second substrate adhered to the second surface of the first substrate and including a penetration part formed to accommodate the plurality of electronic elements mounted on the second surface of the first substrate and a second ground conductor connected to the first ground conductor; a molded portion encapsulating the plurality of electronic elements mounted on the first surface of the first substrate; and a shielding layer formed on outer surfaces of the molded portion and the first substrate and at least a portion of a side surface of the second substrate to shield electromagnetic waves.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate including a first surface and a second surface opposing each other, and a first ground conductor disposed on at least the second surface among the first surface and the second surface;
a plurality of electronic elements mounted on the first surface and the second surface of the first substrate;
a second substrate adhered to the second surface of the first substrate, the second substrate including a penetration part formed to accommodate the plurality of electronic elements mounted on the second surface of the first substrate, and the second substrate including a second ground conductor connected to the first ground conductor;
a molded portion encapsulating the plurality of electronic elements mounted on the first surface of the first substrate; and
a shielding layer formed on outer surfaces of the molded portion and the first substrate and at least a portion of a side surface of the second substrate to shield electromagnetic waves,
wherein the shielding layer is connected directly to the second ground conductor of the second substrate.

2. The semiconductor package of claim 1 , wherein the second ground conductor of the second substrate includes:
a first connection conductor connected to the first ground conductor;
an internal ground conductor formed on an internal layer of the second substrate and connected to the shielding layer;
a second connection conductor formed for an external connection; and
a conductor via connecting the first connection conductor, the internal ground conductor, and the second connection conductor to one another.

3. The semiconductor package of claim 1 , wherein the second ground conductor of the second substrate includes:
a first connection conductor connected to the first ground conductor;
a first internal ground conductor formed on a first internal layer of the second substrate;
a second internal ground conductor formed on a second internal layer of the second substrate;
a second connection conductor formed for an external connection; and
a conductor via connecting the first connection conductor, the first internal ground conductor, the second internal ground conductor, and the second connection conductor to one another,
at least one of the first and second internal ground conductors being connected to the shielding layer.

4. The semiconductor package of claim 3 , wherein the second substrate includes a first shield via formed therein to be spaced apart from the shielding layer formed on the side surface of the substrate, and connecting the first and second internal ground conductors to each other.

5. The semiconductor package of claim 3 , wherein the second substrate further includes a shield via disposed adjacently to the penetration part of the second substrate,
the shielding via including:
a first conductor formed on the first internal layer;
a second conductor formed on the second internal layer; and
a second shield via connecting the first and second conductors to each other.

6. A semiconductor package comprising:
a first substrate including a first surface and a second surface opposing each other, and a first ground conductor and a first signal conductor which are separately formed on at least the second surface among the first surface and the second surface of the first substrate;
a plurality of electronic elements mounted on the first surface and the second surface of the first substrate to thereby be connected to the first signal conductor;
a second substrate adhered to the second surface of the first substrate, the second substrate including a penetration part formed to accommodate the plurality of electronic elements mounted on the second surface of the first substrate, and the second substrate including a second ground conductor and a second signal conductor formed separately from each other in the second substrate, the second ground conductor connected to the first ground conductor, and the second signal conductor connected to the first signal conductor;
a molded portion encapsulating the plurality of electronic elements mounted on the first surface of the first substrate;
a shielding layer formed on outer surfaces of the molded portion and the first substrate and at least a portion of a side surface of the second substrate to shield electromagnetic waves; and
an insulating layer disposed between the first and second substrates,
wherein the shielding layer is connected directly to the second ground conductor of the second substrate.

7. The semiconductor package of claim 6 , wherein the second ground conductor and the second signal conductor of the second substrate are at least disposed in a row, and
the second ground conductor of the second substrate includes:
a first connection conductor connected to the first ground conductor;
an internal ground conductor formed on an internal layer of the second substrate and connected to the shielding layer;
a second connection conductor formed for an external connection; and
a conductor via connecting the first connection conductor, the internal ground conductor, and the second connection conductor to one another.

8. The semiconductor package of claim 6 , wherein the second ground conductor and the second signal conductor of the second substrate are at least disposed in a row, and
the second ground conductor includes:
a first connection conductor connected to the first ground conductor;
a first internal ground conductor formed on a first internal layer of the second substrate;
a second internal ground conductor formed on a second internal layer of the second substrate;
a second connection conductor formed for an external connection; and
a conductor via connecting the first connection conductor, the first internal ground conductor, the second internal ground conductor, and the second connection conductor to one another,
at least one of the first and second internal ground conductors being connected to the shielding layer.

9. The semiconductor package of claim 8 , wherein the second substrate includes a first shield via formed therein to be spaced apart from the shielding layer formed on the side surface of the substrate, and connecting the first and second internal ground conductors to each other.

10. The semiconductor package of claim 8 , wherein the second substrate further includes a shield via disposed adjacently to the penetration part of the second substrate,
the shielding via including:
a first conductor formed on the first internal layer;
a second conductor formed on the second internal layer; and
a second shield via connecting the first and second conductors to each other.

Assignees

• Samsung Electro Mech

Inventors

• Jeon Young Ho
• Lee Il Hyeong

Classifications

• H10W42/284

  shielding resins · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title