Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
US9436594B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9436594-B2 |
| Application number | US-201113117873-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 27, 2011 |
| Priority date | May 27, 2011 |
| Publication date | Sep 6, 2016 |
| Grant date | Sep 6, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Method and apparatus for writing data to a non-volatile memory device, such as a solid state drive (SSD). In accordance with various embodiments, a host write command is serviced by writing a newer copy of user data to a first selected empty physical location in a non-volatile memory, and by concurrently overwriting an older copy of said user data previously stored to a different, second selected occupied physical location of the non-volatile memory.
Opening claim text (preview).
What is claimed is: 1. A method comprising: receiving a host write command from a host device to write a newer copy of user data to a non-volatile memory; temporarily storing the newer copy of the user data in a local buffer; searching the non-volatile memory to locate an older, previously stored copy of the user data; and servicing the host write command by transferring the newer copy of user data from the local buffer to a first selected empty physical location in the non-volatile memory and by concurrently overwriting rubout data onto the older, previously stored copy of the user data stored to a different, second selected occupied physical location in the non-volatile memory, wherein the rubout data are not subsequently erased from the different, second selected occupied physical location in the non-volatile memory during the servicing of the host write command, the different, second physical location comprising a plurality of multi-level cells (MLCs) each adapted to store multiple bits, with a first bit in each MLC in the different, second physical location forming a portion of the older, previously stored copy of the user data and a second bit in each MLC in the different, second physical location forming a portion of a different, second set of user data, the rubout data overwritten by selectively adding charge to the MLCs to alter the bits in the older, previously stored copy of the user data without affecting the bits in the second set of user data. 2. The method of claim 1 , wherein the newer copy of user data is a latest version of a data block having a selected logical address, and the newer copy is the only copy of the user data having the selected logical address in the memory at a conclusion of the servicing of the host write command. 3. The method of claim 1 , further comprising forwarding a command complete status to the host device to signify completion of the servicing of the host write command, and subsequently performing a garbage collection operation to erase the rubout data from the different, second physical location in the non-volatile memory. 4. The method of claim 1 , in which the first and second selected locations are disposed in different erasure blocks of a flash memory array, and the older, previously stored copy of the user data is overwritten in such a way that at least two flash memory cells in the second selected location are overwritten so as to store a maximum amount of charge therein. 5. The method of claim 1 , in which the older, previously stored copy of the user data is encrypted using a first encryption key and the newer copy is encrypted using a different, second encryption key, and the servicing step further comprises purging the first encryption key from the memory. 6. The method of claim 1 , wherein the local buffer is a local volatile memory coupled to the non-volatile memory and the non-volatile memory is a flash memory. 7. The method of claim 1 , in which the servicing of the host write command comprises adding charge to floating gates of the memory cells in the second selected location without removing any charge from said floating gates during the servicing of the host write command. 8. The method of claim 1 , in which the servicing step comprises generating metadata associated with the storage of the newer copy of the user data in the first selected location, and storing said metadata in a memory. 9. The method of claim 1 , in which the searching step locates a second older, previously stored copy of the user data stored in a different, third selected location in the non-volatile memory, and the servicing step further comprises concurrently overwriting second older, previously stored copy of said user data with second rubout data without subsequently erasing the second rubout data prior to completion of the servicing of the host write command. 10. An apparatus comprising: a non-volatile memory which stores an older copy of user data in a first selected location; and a control circuit which, responsive to receipt of a host write command from a host device to write a newer copy of the user data to the non-volatile memory, temporarily stores the newer copy of the user data in a local buffer, searches the non-volatile memory to locate an older, previously stored copy of the user data, and transfers the newer copy of the user data from the local buffer to a second selected empty physical location in the non-volatile memory and concurrently overwrites rubout data onto the older, previously stored copy of the user data in the first selected location without performing an associated erasure of the rubout data during the servicing of the host write command, the first selected location configured as a plurality of multi-level cells (MLCs) each having a multi-bit programming state so that a first bit of each MLC corresponds to a bit value of the older, previously stored copy of the user data and a second bit of each MLC corresponds to a bit value of a second set of user data, the overwriting of the rubout data onto the older, previously stored copy of the user data comprising selectively adding charge to the MLCs so that the MLCs have new multi-bit programming states that still correspond to the bit values of the second set of data. 11. The apparatus of claim 10 , in which control circuit accesses metadata to identify the first selected location in which the older copy of the user data is stored, generates second metadata which identifies the second selected location in which the newer copy of user data is stored, and stores the second metadata in the memory. 12. The apparatus of claim 10 , the control circuit further adapted to transmit a write complete status to the host device to signify completion of the host write command after the writing of the rubout data to the first selected location and after the writing of the newer copy of the user data to the second selected location, the control circuit further adapted to erase the rubout data from the first selected location after the transmission of the write complete status. 13. The apparatus of claim 10 , in which the control circuit subsequently directs an erasure of each memory cell in the first selected location to remove accumulated charge from the memory cells in the first selected location and to place the memory cells in the first selected location in condition to store new data responsive to a subsequent host write command. 14. The apparatus of claim 10 , in which the non-volatile memory is characterized as a flash memory array arranged as a plurality of erasure blocks, the first selected location disposed within a first erasure block of said plurality, the second selected location disposed in a different, second erasure block of said plurality, and the control circuit subsequently schedules a garbage collection operation upon a garbage collection unit that includes the first erasure block independently of the servicing of the host write command. 15. The apparatus of claim 10 , in which the control circuit further operates to generate metadata associated with the storage of the newer copy of the user data in the second selected location, and directs the storage of said metadata in a memory. 16. A data storage device, comprising: a flash memory array having a first selected location that comprises a plurality of multi-level cells (MLCs) each having a multi-bit programmed state where a first bit of the multi-bit programmed state of each MLC corresponds to a bit value in an older, previously stored copy of user data and a second bit of the multi-bit programmed state of each MLC corresponds to a bit value of a second
management of metadata or control data · CPC title
in block erasable memory, e.g. flash memory · CPC title
Logical to physical mapping or translation of blocks or pages · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.