Quantum processor

Patent metadata

Field	Value
Publication number	US-9779360-B2
Application number	US-201615199532-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Mar 24, 2008
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

First claim

The invention claimed is:

1. A quantum processor comprising:
a plurality of qubits and couplers that forms a topology on multiple layers of a chip to embed two complete K8 graphs, the topology comprising:
a first set of sub-topologies of qubits and couplers, the first set of sub-topologies comprising three sub-topologies, each of the three sub-topologies comprising:
a respective first set of qubits;
a respective second set of qubits, each of the qubits in the respective second set of qubits having a respective portion which crosses a respective portion of at least one of the qubits in the respective first set of qubits; and
a respective first set of couplers, each coupler in the respective first set of couplers selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits to embed a complete K4 graph;

the first set of sub-topologies comprising a second set of couplers, each coupler in the second set of couplers selectively operable to directly communicatively couple one of the qubits in one of the sub-topologies in the first set of sub-topologies to one of the qubits in another one of the sub-topologies in the first set of sub-topologies to embed a complete K8 graph in the three sub-topologies of the first set of sub-topologies;
a second set of sub-topologies of qubits and couplers, the second set of sub-topologies comprising three sub-topologies, each of the three sub-topologies comprising:
a respective first set of qubits;
a respective second set of qubits, each of the qubits in the respective second set of qubits having a respective portion which crosses a respective portion of at least one of the qubits in the respective first set of qubits; and
a respective first set of couplers, each coupler in the respective first set of couplers selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits to embed a complete K4 graph;

the second set of sub-topologies comprising a second set of couplers, each coupler in the second set of couplers selectively operable to directly communicatively couple one of the qubits in one of the sub-topologies in the second set of sub-topologies to one of the qubits in another one of the sub-topologies in the second set of sub-topologies to embed a complete K8 graph in the three sub-topologies of the second set of sub-topologies;
the topology comprising a third set of couplers, each coupler in the third set of couplers selectively operable to directly communicatively couple one of the qubits in one of the sub-topologies in the first set of sub-topologies to one of the qubits in one of the sub-topologies in the second set of sub-topologies to embed two complete K8 graphs.

2. The quantum processor of claim 1 wherein a plurality of nodes of the two complete K8 graphs are embedded into a respective qubit, and one or more edges of the two complete K8 graphs are embedded into a respective coupler.

3. The quantum processor of claim 1 wherein the quantum processor is a superconducting quantum processor chip, and each qubit in the first and the second sets of qubits in the first set of sub-topologies and each qubit in the first and the second set of qubits in the second set of sub-topologies is a superconducting qubit.

4. The quantum processor of claim 3 wherein each qubit in the first and the second sets of qubits in the first set of sub-topologies and in the first and the second set of qubits in the second set of sub-topologies comprises an elongated loop of superconducting material interrupted by at least one Josephson junction.

5. The quantum processor of claim 4 wherein each qubit in the first set of qubits in the first set of sub-topologies is laid out horizontally, each qubit in the second set of qubits in the first set of sub-topologies is laid out vertically, each qubit in the first set of qubits in the second set of sub-topologies is laid out horizontally, and each qubit in the second set of qubits in the second set of sub-topologies is laid out vertically.

6. The quantum processor of claim 4 wherein the respective portion of the qubits in the respective first set of qubits is a portion of the respective elongated loop of superconducting material and which resides in a first metal layer, and the respective portion of the qubits in the respective second set of qubits is a portion of the respective elongated loop of superconducting material, and which resides in a second metal layer, the second metal layer different from the first metal layer.

7. The quantum processor of claim 4 wherein the second metal layer at least one of underlies or overlies the first metal layer.

8. The quantum processor of claim 4 wherein the respective portion of the qubits of the respective second set of qubits cross the respective portion of the qubits in the respective first set of qubits at a right angle.

9. The quantum processor of claim 1 wherein each coupler in the first set of couplers in each sub-topology in the first set of sub-topologies, each coupler in the first set of couplers in each sub-topology in the second set of sub-topologies, each coupler in the second set of couplers in the first and the second set of sub-topologies, and each coupler in the third set of couplers is selectively operable to couple qubits by at least one of a ferromagnetic coupling, an anti-ferromagnetic coupling, a zero coupling, or a transverse coupling.

10. The quantum processor of claim 1 wherein the sub-topologies in the first and the second set of sub-topologies are arranged to form a grid.

11. The quantum processor of claim 1 further comprising a third set of sub-topologies of qubits and couplers, the third set of sub-topologies comprising four sub-topologies arranged in a 2×2 grid, each of the four sub-topologies comprising:
a respective first set of qubits;
a respective second set of qubits, each of the qubits in the respective second set of qubits having a respective portion which crosses a respective portion of at least one of the qubits in the respective first set of qubits; and
a respective first set of couplers, each coupler in the respective first set of couplers selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits to embed a bipartite graph;
the third set of sub-topologies comprising a second set of couplers, each coupler in the second set of couplers selectively operable to directly communicatively couple one of the qubits in one of the sub-topologies in the third set of sub-topologies to a qubits in another one of the sub-topologies in the third set of sub-topologies to embed a complete bipartite graph in the four sub-topologies of the third set of sub-topologies; and
wherein each coupler in the third set of couplers is selectively operable to directly communicatively couples one of the qubits in one of the sub-topologies in the first set of sub-topologies to one of the qubits in one of the sub-topologies in the third set of sub-topologies and to communicatively couple one of the qubits in one of the sub-topologies in the second set of sub-topologies to one of the qubits in one of the sub-topologies in the third set of sub-topologies to embed a complete K16 graph.

12. The quantum processor of claim 11 wherein a plurality of nodes of the complete K16 graph are embedded into a respective qubit, and one or more edges of the complete K16 graph are embedded into a respective coupler.

13. The quantum process

Assignees

• D Wave Systems Inc

Inventors

• Bunyk Paul
• Maibaum Felix

Classifications

• G06F15/82

  data or demand driven · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G01R1/06755

  Material aspects · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title