Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements

Patent metadata

Field	Value
Publication number	US-9779202-B2
Application number	US-201514867226-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Jun 22, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

First claim

What is claimed is:

1. A method, comprising:
obtaining a first set of wafer geometry measurements of a wafer utilizing a geometry measurement tool prior to the wafer undergoing a fabrication process;
obtaining a second set of wafer geometry measurements of the wafer utilizing the geometry measurement tool after the fabrication process;
calculating, utilizing one or more processors, a shape-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
analyzing, utilizing the one or more processors, the shape-change map to detect an asymmetric component induced to wafer geometry by the fabrication process, wherein said analyzing step further comprises:
calculating an in-plane distortion of the wafer at least partially based on the shape-change map;
generating a filtered in-plane distortion map by removing symmetric components from the in-plane distortion of the wafer;
detecting the asymmetric component at least partially based on the filtered in-plane distortion map;
generating a local shape curvature map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
detecting the asymmetric component at least partially based on the local shape curvature map;
determining an asymmetry factor based on a weight of non-symmetric components contained within the local shape curvature map;
determining a magnitude of the in-plane distortion of the wafer;
quantifying the impact of the asymmetric component on overlay based on a product of the asymmetry factor and the magnitude of the in-plane distortion of the wafer; and

estimating, utilizing the one or more processors, an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

2. The method of claim 1 , wherein said detecting the asymmetric component further comprises:
generating a filtered local shape curvature map by removing symmetric components from the local shape curvature map; and
detecting the asymmetric component at least partially based on the filtered local shape curvature map.

3. The method of claim 2 , further comprising:
quantifying an impact of the asymmetric component on overlay.

4. The method of claim 1 , further comprising:
classifying the wafer into one of a plurality of wafer groups based on at least one of: the filtered in-plane distortion map, the filtered local shape curvature map, and the impact of the asymmetric component on overlay.

5. The method of claim 1 , further comprising:
reporting at least one of: the filtered in-plane distortion map, the filtered local shape curvature map, and the impact of the asymmetric component on overlay in a feedback control for controlling a fabrication process tool that performed the fabrication process.

6. The method of claim 1 , further comprising:
reporting at least one of: the filtered in-plane distortion map, the filtered local shape curvature map, and the impact of the asymmetric component on overlay in a feed forward control for controlling a subsequent fabrication process tool.

7. A method, comprising:
obtaining a first set of wafer geometry measurements of a wafer utilizing a geometry measurement tool prior to the wafer undergoing a fabrication process;
obtaining a second set of wafer geometry measurements of the wafer utilizing the geometry measurement tool after the fabrication process;
calculating, utilizing one or more processors, a shape-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
generating at least one of: an in-plane distortion map and a local shape curvature map of the wafer at least partially based on the shape-change map; and
detecting a process-induced asymmetric component at least partially based on at least one of: the in-plane distortion map and the local shape curvature map of the wafer, wherein said detecting the process-induced asymmetric component further comprises:
determining an asymmetry factor based on a weight of non-symmetric components contained within the local shape curvature map;
determining a high-frequency factor based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; and
quantifying an impact of the process-induced asymmetric component on overlay based on a product of the asymmetry factor and the high-frequency factor.

8. The method of claim 7 , wherein said detecting the process-induced asymmetric component further comprises:
generating a filtered local shape curvature map by removing symmetric components from the local shape curvature map; and
detecting the process-induced asymmetric component at least partially based on the filtered local shape curvature map.

9. The method of claim 7 , wherein the high-frequency factor includes a magnitude of the in-plane distortion of the wafer.

10. The method of claim 7 , further comprising:
reporting the impact of the process-induced asymmetric component on overlay in a feedback control for controlling a fabrication process tool that performed the fabrication process.

11. The method of claim 7 , further comprising:
reporting the impact of the process-induced asymmetric component on overlay in a feed forward control for controlling a subsequent fabrication process tool.

12. A system, comprising:
a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process; and
a processor in communication with the geometry measurement tool, the processor configured to:
calculate a shape-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
analyze the shape-change map to detect an asymmetric component induced to wafer geometry by the fabrication process;
calculate an in-plane distortion of the wafer at least partially based on the shape-change map;
generate a filtered in-plane distortion map by removing symmetric components from the in-plane distortion of the wafer;
detect the asymmetric component at least partially based on the filtered in-plane distortion map;
generate a local shape curvature map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
detect the asymmetric component at least partially based on the local shape curvature map;
determine an asymmetry factor based on a weight of non-symmetric components contained within the local shape curvature map;
determine a magnitude of the in-plane distortion of the wafer;
quantify the impact of the asymmetric component on overlay based on a product of the asymmetry factor and the magnitude of the in-plane distortion of the wafer; and
estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

13. The system of claim 12 , wherein the processor is further configured to:
generate a filtered local shape curvature map by removing symmetric components from the local shape curvature map; and
detect the asymmetric component at least partially based on the filtered local shape curvature map.

14. The system of claim 13 , wherein the processor is further configured to:
quantify an impact of the asymmetric component on overlay.

15. The system of claim 12 , wherein the processor is further configured to:
classify the wafer into one of a plurality of wafer groups based on at least one o

Assignees

• Kla Tencor Corp

Inventors

• Vukkadala Pradeep
• Sinha Jaydeep
• Kim Jong-Hoon

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F7/70633 Primary

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• G03F1/44

  Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title