Preventing timing violations

Patent metadata

Field	Value
Publication number	US-9774329-B2
Application number	US-201415026583-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Oct 2, 2013
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

First claim

The invention claimed is:

1. Apparatus, comprising
a clock adapted to provide a clock signal, wherein the clock signal alternates with a cycle between a first level and a second level different from the first level if a timing violation is not detected;
a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level and is closed for the first signal when the clock is at the second level;
a second combinational logic adapted to output a second signal based on the first signal passed through the first latch;
a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level and is closed for the second signal when the clock is at the first level;
wherein the first latch is adapted to be clocked such that the first latch is closed for the first signal when the clock is at the second level;
wherein the second latch is adapted to be clocked such that the second latch is closed for the second signal when the clock is at the first level;
wherein the first latch and the second latch are collectively clocked, and wherein the clock signal for the first and the second latches is synchronized;
a detecting means adapted to detect the timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and of the second signal at the second latch when the clock signal is at the second level; and
a time stretching means adapted to stretch, if the timing violation is detected, the clock collectively for both the first latch and the second latch such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to the cycle.

2. The apparatus according to claim 1 , further comprising
a first combinational logic adapted to output the first signal;
wherein the second combinational logic is adapted to output the second signal at a second output.

3. The apparatus according to claim 2 , wherein
the second latch is directly connected to the second output;
the first combinational logic is adapted to output the first signal at a first output; and
the first latch is directly connected to the first output.

4. The apparatus according to claim 1 , wherein
the clock is adapted to provide the clock signal and an inverse clock signal, wherein the inverse clock signal is at a first inverse level when the clock signal is at the first level, and the inverse clock signal is at a second inverse level different from the first inverse level when the clock signal is at the second level; and
the first latch is adapted to check if the clock signal is at the first level and to pass the first signal if the clock signal is at the first level, and the second latch is adapted to check if the inverse clock signal is at the second inverse level and to pass the second signal if the clock signal is at the second inverse level.

5. The apparatus according to claim 4 , wherein
the first level is the same as the second inverse level; and
the second level is the same as the first inverse level.

6. The apparatus according to claim 4 , wherein
the clock is adapted to output the clock signal at a clock output;
the first latch is directly connected to the clock output and adapted to check if the clock signal is at the first level and to pass the first signal if the clock signal is at the first level; and,
the clock is adapted to output the inverse clock signal at an inverse clock output, the second latch is directly connected to the inverse clock output, and the second latch is adapted to check if the inverse clock signal is at the second inverse level and to pass the second signal if the inverse clock signal is at the second inverse level.

7. The apparatus according to claim 1 , wherein
the clock is adapted to output the clock signal at a clock output;
the first latch is directly connected to the clock output and adapted to check if the clock signal is at the first level and to pass the first signal if the clock signal is at the first level; and
the second latch is directly connected to the clock output, and the second latch is adapted to check if the clock signal is at the second level and to pass the second signal if the clock signal is at the second level.

8. The apparatus according to claim 1 , comprising
plural combinational logics consisting of at least one odd-numbered combinational logic and at least one even-numbered combinational logic including the second combinational logic;
plural latches consisting of odd-numbered latches including the first latch and even-numbered latches including the second latch; wherein
each of the odd-numbered latches except for the first latch is adapted to pass a respective signal output from a corresponding one of the at least one odd-numbered combinational logic, and the first latch is adapted to pass the first signal;
each of the even-numbered latches is adapted to pass a respective signal output from a corresponding one of the at least one even-numbered combinational logic;
each of the at least one odd-numbered combinational logic is adapted to output the respective signal based on the signal passed through a directly precedent one of the even-numbered latches;
each of the at least one even-numbered combinational logic is adapted to output the respective signal based on the signal passed in a directly precedent one of the odd-numbered latches;
each of the odd-numbered latches is adapted to pass the respective signal output by the corresponding odd-numbered combinational logic when the clock signal is at the first level;
each of the even-numbered latches is adapted to pass the respective signal output by the corresponding even-numbered combinational logic when the clock signal is at the second level.

9. The apparatus according to claim 1 , further comprising a third latch adapted to pass a third signal when the clock signal is at the first level;
a fourth combinational logic adapted to output a fourth signal based on the third signal passed through the third latch;
a fourth latch adapted to pass the fourth signal when the clock is at the second level; and
a third combinational logic adapted to output the third signal based upon the second signal passed through the second latch.

10. Apparatus according to claim 1 , wherein
the first latch is adapted to store the first signal when the clock alternates from the first level to the second level and to maintain the first signal until the clock alternates again to the first level; and/or
the second latch is adapted to store the second signal when the clock alternates from the second level to the first level and to maintain the second signal until the clock alternates again to the second level.

11. The apparatus according to claim 1 , further comprising
a third latch adapted to pass a third signal when the clock signal is at the first level;
a fourth combinational logic adapted to output a fourth signal based on the third signal passed through the third latch; and
a fourth latch adapted to pass the fourth signal when the clock is at the first second;
wherein the first signal comprises the fourth signal passed through the fourth latch.

12. Apparatus, comprising
a clock adapted to provide a clock signal, wherein the clock signal alternates with a cycle between a first level and a second level different from the first level if a timing violation is not detected;
a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level and is closed for the first signal when the clock is at the s

Assignees

• Aalto Univ Found
• Teknologian Tutkimuskeskus Vtt Oy
• Minima Processor Oy

Inventors

• Mäkipää Jani
• Koskinen Lauri
• Turnquist Matthew
• Hiienkari Markus

Classifications

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K5/06

  by the use of delay lines or other analogue delay elements · CPC title