Low power threshold integrated micro-plasma limiter

Patent metadata

Field	Value
Publication number	US-9774067-B2
Application number	US-201514708838-A
Country	US
Kind code	B2
Filing date	May 11, 2015
Priority date	May 31, 2012
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.

First claim

What is claimed is:

1. A plasma power limiter comprising:
a signal substrate having a first side and a second side, said signal substrate including an input signal line formed on the first side of the signal substrate, a signal transmission line formed on the second side of the signal substrate and an output signal line formed on the first side of the signal substrate, wherein an input signal at a power level less than a threshold power level propagating on the input signal line is electrically coupled to the signal transmission line and a signal propagating on the signal transmission line is electrically coupled to the output signal line as an output signal with low loss; and
a ground substrate having a first side and a second side, said ground substrate being bonded to the signal substrate to form a hermetically sealed cavity therebetween, where the second side of the signal substrate faces the second side of the ground substrate within the cavity, said ground substrate including a ground metal layer formed on the second side of the ground substrate, said cavity being filled with an ionizable gas, wherein the signal propagating on the input signal line at a power level greater than the threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, which limits a power of the output signal coupled to the output signal line, wherein the power limiter is fabricated using wafer-level fabrication techniques where the power limiter is formed at the same time as other circuit elements.

2. The power limiter according to claim 1 wherein the signal transmission line is a high impedance transmission line including a high impedance element having a higher impedance than the input signal line and the output signal line, said power limiter including impedance matching elements for impedance matching the input and output signal lines to the high impedance element.

3. The power limiter according to claim 1 further comprising a plasma pilot light electrode formed on the second side of the signal substrate and a plasma pilot light bias line formed on the first side of the signal substrate and being electrically coupled through the signal substrate to the pilot light electrode, wherein a bias signal provided on the pilot light bias line causes the pilot light electrode to generate a low electron density plasma discharge in the cavity that reduces the threshold power level.

4. The power limiter according to claim 1 further comprising a DC voltage bias line formed on the first side of the signal substrate and being electrically coupled through the signal substrate to the signal transmission line, wherein a bias voltage provided on the bias line causes the signal transmission to generate a low electron density plasma discharge in the cavity that reduces the threshold power level.

5. The power limiter according to claim 1 further comprising an electrical bias circuit that provides an electrical bias to the input signal line that increases the ionization state of the gas in the cavity.

6. The power limiter according to claim 5 wherein the bias circuit includes an alternating current signal electrically coupled to the input signal line through a direct current blocking filter, a direct current source electrically coupled to the input signal line through an alternating current signal blocking filter, and an output signal load electrically coupled to the output signal line through a direct current blocking filter.

7. The power limiter according to claim 1 wherein the input signal line and the output signal line are capacitively coupled to the signal transmission line through the signal substrate.

8. The power limiter according to claim 1 wherein the input signal line and the output signal line are electrically coupled to the signal transmission line by metal vias extending through the signal substrate.

9. The power limiter according to claim 1 wherein the power limiter is part of a receiver front end between an antenna and a low noise amplifier.

10. The power limiter according to claim 1 wherein the power limiter is one of a plurality of plasma power limiters electrically coupled in series.

11. The power limiter according to claim 10 wherein the plurality of plasma power limiters have different activation thresholds.

12. A plasma power limiter comprising:
a signal substrate having a first side and a second side, said signal substrate including an input signal line formed on the first side of the signal substrate, a split ring resonator formed on the second side of the signal substrate and an output signal line formed on the first side of the signal substrate, said split ring resonator including a gap, wherein an input signal at a power level less than a threshold power level propagating on the input signal line is electrically coupled to the split ring resonator and a signal propagating on the split ring resonator is electrically coupled to the output signal line with low loss; and
a ground substrate having a first side and a second side, said ground substrate being bonded to the signal substrate to form a sealed cavity therebetween, where the second side of the signal substrate faces the second side of the ground substrate within the cavity, said ground substrate including a ground metal layer formed on the second side of the ground substrate, said cavity being filled with an ionizable gas, wherein the input signal propagating on the input signal line at a power level greater than the threshold power level causes the split ring resonator to generate a large voltage swing across the gap that ionizes the gas within the cavity and generates a plasma discharge, which limits power of the output signal coupled to the output signal line.

13. The power limiter according to claim 12 wherein the input signal line and the output signal line are capacitively coupled to the split ring resonator through the signal substrate.

14. The power limiter according to claim 12 further comprising a plasma pilot light electrode formed on the second side of the signal substrate and a plasma pilot light bias line formed on the first side of the signal substrate and being electrically coupled through the signal substrate to the pilot light electrode, wherein a bias signal provided on the pilot light bias line causes the pilot light electrode to generate a low electron density plasma discharge in the cavity that reduces the threshold power level.

15. The power limiter according to claim 12 further comprising a DC voltage bias line formed on the first side of the signal substrate and being electrically coupled through the signal substrate to the split ring resonator, wherein a bias signal provided on the bias line causes the split ring resonator to generate a low electron density plasma discharge in the cavity that reduces the threshold power level.

16. A plasma power limiter comprising:
a signal substrate having a first side and a second side, said signal substrate including an input signal line formed on the first side of the signal substrate, a high impedance transmission line having a high impedance element formed on the second side of the signal substrate and being electrically coupled and impedance matched to the input signal line, and an output signal line formed on the first side of the signal substrate and being electrically coupled and impedance matched to the high impedance transmission line, wherein an input signal at a power level less than a threshold power level propagating on the input signal line is electrically coupled to the high impedance transmission line and a signal propaga

Assignees

• Northrop Grumman Systems Corp

Inventors

• Poust Benjamin D
• Battung Michael Conrad
• Ferizovic Dino
• Chang-Chien Patty P

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01T19/04

  having pointed electrodes · CPC title

• H03G11/004

  using discharge tubes (H03G11/008 takes precedence) · CPC title

• H03G11/002

  without controlling loop (H03G11/004, H03G11/006, H03G11/008, H03G11/02, H03G11/04, H03G11/06, H03G11/08 take precedence) · CPC title

• H01T4/16

  having a plurality of gaps arranged in series · CPC title