Memory cell array structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9773844-B2
Application number	US-201514970602-A
Country	US
Kind code	B2
Filing date	Dec 16, 2015
Priority date	Jul 24, 2013
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

First claim

What is claimed is:

1. An array of memory cells, comprising:
a first stack structure coupled to a conductive material via an exposed conductive surface of the first stack structure,
wherein the exposed conductive surface is the only exposed portion of the first stack structure; and

an electrically inactive stack structure located at an edge of the first stack structure, wherein the electrically inactive stack structure is physically isolated from the conductive material to which the first stack structure is coupled and is connected to only the first conductive material.

2. The array of claim 1 , wherein the first stack structure further comprises:
a select element between a first electrode and a second electrode; and
a memory element between the second electrode and a third electrode.

3. The array of claim 1 , further comprising a second stack structure formed on the first stack structure, each of the first and the second stack structure comprising the conductive material.

4. The array of claim 1 , further comprising a dielectric material between the first stack structure and the electrically inactive stack structure.

5. The array of claim 1 , wherein the first stack structure comprises a different dimension than the electrically inactive stack structure.

6. The array of claim 1 , wherein the array is a cross-point array.

7. An array of memory cells, comprising:
a first electrically active stack structure coupled to a conductive material via an exposed conductive surface of the first electrically active stack structure,
wherein the exposed conductive surface is the only exposed portion of the first stack structure;

a second electrically active stack structure coupled to the first electrically active stack structure and coupled to the conductive material;
a first electrically inactive stack structure; and
a second electrically inactive stack structure,
wherein the first and the second electrically inactive stack structures are physically isolated from the conductive material to which the first and the second electrically active stack structures are coupled and are connected to only the first conductive material.

8. The array of claim 7 , further comprising:
the first electrically inactive stack structure located at an outer edge of the first electrically active stack structure; and
the second electrically inactive stack structure located at an outer edge of the second electrically active stack structure.

9. The array of claim 7 , further comprising the second electrically active stack structure coupled to the first electrically active stack structure via the exposed conductive surface of the first electrically active stack.

10. The array of claim 7 , further comprising at least one of the first electrically inactive stack structure and the second electrically inactive stack structure being wider than each of the first electrically active stack structure and the second electrically active stack structure.

11. The array of claim 7 , further comprising:
each of the first and the second electrically inactive stack structures located at a different outer edge of the first electrically active stack structure; and
each of a third and a fourth electrically inactive stack structure located at a different outer edge of the second stack structure and physically isolated from a second conductive material.

12. The array of claim 7 , wherein the array is a three-dimensional cross-point array of memory cells.

13. A method of forming an array of memory cells, comprising:
forming a material over a first dummy material stack structure to electrically inactivate the first dummy material stack structure and physically isolate the first dummy material stack structure from a conductive material to which a first electrically active stack structure is coupled via an exposed conductive surface of the first electrically active stack structure,
wherein the exposed conductive surface is the only exposed portion of the first stack structure, and wherein the first dummy material stack structure is connected to only the conductive material.

14. The method of claim 13 , further comprising forming a second electrically active stack structure over the first electrically active stack structure.

15. The method of claim 13 , further comprising:
performing a first chop sequence on the first electrically active stack structure and the first dummy material stack structure; and
forming a second electrically active stack structure over the first electrically active stack structure.

16. The method of claim 15 , further comprising:
forming a second dummy stack structure located at an edge of the second electrically active stack structure; and
performing a second chop sequence on the second electrically active stack structure and the second dummy stack structure to electrically inactivate the second dummy memory cell stack structure.

17. The method of claim 16 , wherein the second chop sequence comprises:
patterning the second electrically active stack structure and the second dummy stack structure to expose the second dummy stack structure;
removing a portion of the second dummy stack structure via an etch;
forming a dielectric material over the second electrically active stack structure, the second dummy stack structure, and into spaces formed during the dummy stack structure etch; and
planarizing the dielectric material to expose a conductive portion of the second electrically active stack structure.

18. The method of claim 13 , further comprising:
patterning the first electrically active stack structure and the first dummy material stack structure to expose the first dummy material stack structure;
removing a portion of the first dummy material stack structure; and
forming the material over the first dummy material stack structure.

19. The method of claim 18 , wherein removing a portion of the dummy material stack structure includes etching a portion of the dummy material stack structure via a dry etch.

20. The method of claim 18 , wherein patterning the first electrically active stack structure and the first dummy material stack structure to expose the first dummy material stack structure comprises:
forming a photoresist material over the first electrically active stack structure; and
exposing the photoresist material over the first dummy material stack structure.

Assignees

• Micron Technology Inc

Inventors

• Ravasio Marcello
• Sciarrillo Samuele
• Somaschini Roberto
• Donadio Gabriel L

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• H01L27/2481 Primary

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic