Nonvolatile semiconductor memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9012969-B2
Application number	US-201113237545-A
Country	US
Kind code	B2
Filing date	Sep 20, 2011
Priority date	Mar 18, 2011
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising:
a semiconductor layer having a first area and a second area;
an active area formed in the semiconductor layer, extending in a first direction, and including a select transistor, a first memory transistor, and a second memory transistor, the select transistor, the first memory transistor, and the second memory transistor being connected in series; and
a device isolation film formed on the semiconductor layer, extending in the first direction, being adjacent to the active area, and having a first height in the first area and a second height higher than the first height in the second area,
the first area including a first end of the first memory transistor facing the second memory transistor and a first part of the device isolation film adjacent thereof, and the second area including a second end of the first memory transistor facing the select transistor and a second part of the device isolation film adjacent thereof.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the first memory transistor and the second memory transistor comprise an electric storage film formed above the active area via a first gate insulating film, and a control gate formed above the electric storage film via a first insulating film,
a top surface of the electric storage film of the second memory transistor is formed at a higher position than the first height, and
a top surface of the electric storage film of the first memory transistor is formed at substantially the same height as the second height at least at the second end of the first memory transistor.

3. The nonvolatile semiconductor memory device according to claim 2 , wherein the electric storage film has a polysilicon film.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein the second area includes the select transistor and a third part of the device insulation film adjacent thereof.

5. The nonvolatile semiconductor memory device according to claim 4 , wherein the first memory transistor and the second memory transistor comprise an electric storage film formed above the active area via a first gate insulating film, and a control gate formed on the electric storage film via a first insulating film,
the select transistor comprises a first gate formed above the active area via a second gate insulating film, a second gate formed above the first gate via a second insulating film, and the second insulating film having a through hole embedded with a conductive film, and
a thickness of the second gate is higher than that of the control gate on the device isolation film.

6. The nonvolatile semiconductor memory device according to claim 4 , wherein the first part of the device isolation film, the second part of the device isolation film, and the third part of the device isolation film are arranged continuously.

7. The nonvolatile semiconductor memory device according to claim 4 , wherein the first part of the device isolation film, the second part of the device isolation film, and the third part of the device isolation film are arranged in the first direction.

8. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a plurality of the active areas are arranged in a second direction crossing to the first direction;
a second word line commonly connected to gates of the second memory transistors arranged in the second direction;
a first word line commonly connected to gates of the first memory transistors arranged in the second direction; and
a select gate line commonly connected to gates of the select transistors arranged in the second direction, wherein
a distance between the second word line and the first word line adjacent to each other is shorter than a distance between the first word line and the select gate line adjacent to each other.

9. The nonvolatile semiconductor memory device according to claim 1 , wherein the first part of the device isolation film and the second part of the device isolation film are arranged continuously.

10. The nonvolatile semiconductor memory device according to claim 1 , wherein the first part of the device isolation film and the second part of the device isolation film are arranged in the first direction.

Assignees

• Kamigaichi Takeshi
• Toshiba Kk

Inventors

• Kamigaichi Takeshi

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/69 Primary

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L29/792

  Electricity · mapped topic

• H01L21/76229

  Electricity · mapped topic