Method for driving semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9240244-B2
Application number	US-201414200430-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 14, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

First claim

The invention claimed is:

1. A method for driving a semiconductor device comprising a memory cell, wherein the memory cell comprises a first transistor, a second transistor and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a bit line, wherein one of a source and a drain of the second transistor is electrically connected to the bit line, and wherein the gate of the second transistor is electrically connected to a first electrode of the capacitor, the method comprising the steps of:
changing the first transistor from an on-state to an off-state to hold data in the memory cell;
changing a potential of a second electrode of the capacitor to turn off the second transistor regardless of a potential of the data; and
changing the potential of the second electrode of the capacitor such that the second transistor is turned on and then electrical charge of the bit line is discharged until the second transistor is turned off.

2. The method for driving a semiconductor device according to claim 1 , wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

3. The method for driving a semiconductor device according to claim 1 , wherein the second transistor is a p-channel transistor.

4. The method for driving a semiconductor device according to claim 1 , wherein the second transistor comprises a channel formation region comprising silicon.

5. The method for driving a semiconductor device according to claim 1 , further comprising the step of:
bringing the bit line into an electrically floating state before changing the potential of the second electrode of the capacitor such that the second transistor is turned on and then electrical charge of the bit line is discharged until the second transistor is turned off.

6. A method for driving a semiconductor device comprising a memory cell, wherein the memory cell comprises a first transistor, a second transistor and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a bit line, wherein one of a source and a drain of the second transistor is electrically connected to the bit line, and wherein the gate of the second transistor is electrically connected to a first electrode of the capacitor, the method comprising the steps of:
changing the first transistor from an on-state to an off-state to hold data in the memory cell, while a first potential is applied to a second electrode of the capacitor;
changing a potential of the second electrode of the capacitor from the first potential to a second potential while holding the data in the memory cell;
applying a first voltage to the bit line while holding the data in the memory cell, after changing the potential of the second electrode of the capacitor from the first potential to the second potential; and
changing the potential of the second electrode of the capacitor from the second potential to the first potential while applying a second voltage to the other of the source and drain of the second transistor, after applying the first voltage to the bit line,
wherein the second voltage is lower than the first voltage.

7. The method for driving a semiconductor device according to claim 6 , wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

8. The method for driving a semiconductor device according to claim 6 , wherein the second transistor is a p-channel transistor.

9. The method for driving a semiconductor device according to claim 6 , wherein the second transistor comprises a channel formation region comprising silicon.

10. The method for driving a semiconductor device according to claim 6 , further comprising the step of:
bringing the bit line into an electrically floating state after applying the first voltage to the bit line and before changing the potential of the second electrode of the capacitor from the second potential to the first potential.

11. A method for driving a semiconductor device comprising a memory cell, wherein the memory cell comprises a first transistor, a second transistor and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a bit line, wherein one of a source and a drain of the second transistor is electrically connected to the bit line, wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line, wherein the gate of the second transistor is electrically connected to a first electrode of the capacitor, wherein a second electrode of the capacitor is electrically connected to a read word line, and wherein the second transistor is a p-channel transistor, the method comprising the steps of:
changing the first transistor from an on-state to an off-state to hold data in the memory cell, while a first potential is applied to the read word line and a potential based on data is applied to the bit line;
changing a potential of the read word line from the first potential to a second potential while holding the data in the memory cell;
applying a first voltage to the bit line while holding the data in the memory cell, after changing the potential of the read word line from the first potential to the second potential; and
changing the potential of the read word line from the second potential to the first potential while applying a second voltage to the power supply line such that the second transistor is turned on and then electrical charge of the bit line is discharged until a potential of the bit line is lowered to a third potential corresponding to the potential based on the data, after applying the first voltage to the bit line.

12. The method for driving a semiconductor device according to claim 11 , wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

13. The method for driving a semiconductor device according to claim 11 , wherein the second transistor comprises a channel formation region comprising silicon.

14. The method for driving a semiconductor device according to claim 11 , further comprising the step of:
bringing the bit line into an electrically floating state after applying the first voltage to the bit line and before changing the potential of the read word line from the second potential to the first potential.

15. A semiconductor device comprising:
a memory cell comprising:
a first transistor;
a second transistor; and
a capacitor; and

an A/D converter,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a bit line,
wherein one of a source and a drain of the second transistor is electrically connected to the bit line,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein the gate of the second transistor is electrically connected to a first electrode of the capacitor,
wherein a second electrode of the capacitor is electrically connected to a read word line, and
wherein the bit line is electrically connected to the A

Assignees

• Semiconductor Energy Lab

Inventors

• Nagatsuka Shuhei
• Inoue Hiroki
• Ishizu Takahiko
• Matsuzaki Takanori
• Shionoiri Yutaka
• Kato Kiyoshi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L29/78696

  Electricity · mapped topic