Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9773707-B2
Application number	US-201514838628-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Jun 23, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a plurality of openings formed in an NMOS device region and a PMOS device region thereon by removing respective sacrificial gates for NMOS devices to be formed in the NMOS device region and PMOS devices to be formed in the PMOS device region;
filling the openings in both the NMOS device region and the PMOS device region with a top metal layer having compressive stress along a direction perpendicular to channels for the NMOS and PMOS devices; and
performing amorphization implantation with respect to the top metal layer in the PMOS device region to release the compressive stress in the top metal layer in the PMOS device region.

2. The method according to claim 1 , wherein the step of filling the openings with a top metal layer comprises the step of:
filling the openings with a top metal layer of tungsten nitride having compressive stress by a PVD process.

3. The method according to claim 2 , wherein the step of filling the openings with a top metal layer of tungsten nitride comprises the step of:
using a tungsten target and nitrogen as reaction sources in the PVD process to fill the openings with the top metal layer of tungsten nitride.

4. The method according to claim 2 , wherein Ge is implanted in the amorphization implantation.

5. The method according to claim 4 , wherein the amorphization implantation is performed with an implantation energy of about 0.5-30 keV at a dosage of about 5E14-5E16/cm 2 .

6. The method according to claim 1 , wherein the step of filling the openings with a top metal layer and performing amorphization implantation comprises the steps of:
filling in the openings a metal layer having compressive stress;
performing planarization;
forming a mask layer covering the NMOS device region;
performing the amorphization implantation;
removing the mask layer; and
removing portions of the metal layer outside the openings to form the top metal layer in the openings.

7. The method according to claim 1 , wherein before filling the openings with the top metal layer, the method further comprises the step of:
forming a high-K gate dielectric layer on inner walls of the openings and then performing thermal annealing.

8. The method according to claim 7 , wherein the thermal annealing is performed at a temperature of about 450° C. for about 15 seconds.

9. The method according to claim 7 , wherein after forming the high-K gate dielectric layer and before filling the openings with the top metal layer, the method further comprises the steps of:
forming a metal barrier layer on the high-K gate dielectric layer; and
forming a metal work function layer on the metal barrier layer.

10. The method according to claim 9 , wherein the metal barrier layer comprises TiN or WN.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Wang Guilei
• Liu Jinbiao
• Gao Jianfeng
• Li Junfeng
• Zhao Chao

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title