Recessing rmg metal gate stack for forming self-aligned contact

Patent metadata

Field	Value
Publication number	US-2016149015-A1
Application number	US-201414550019-A
Country	US
Kind code	A1
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

First claim

1 . A method comprising:
forming a first embedded etch stop layer in a gate dielectric layer and a work-function metal layer of a replacement metal gate (RMG) using ion implantation, wherein the first embedded etch stop layer comprises a layer of dopant atoms embedded at a depth below an upper portion of the gate dielectric layer and an upper portion of the work-function metal layer; removing the upper portion of the gate dielectric layer and the upper portion of the work-function metal layer; removing the first embedded etch stop layer to expose a lower portion of the gate dielectric layer and a lower portion of the work-function metal layer; forming a gate electrode on the lower portion of the gate dielectric layer and the lower portion of the work-function metal layer; and forming a gate cap on the gate electrode, the gate cap having an upper surface that is substantially flush with an upper surface of a spacer adjacent to the RMG and an upper surface of an interlevel dielectric (ILD) layer adjacent to the spacer.

2 . The method of claim 1 , wherein the dopant atoms comprise silicon, carbon, or nitrogen.

3 . (canceled)

4 . The method of claim 1 , wherein the first embedded etch stop layer extends laterally through the spacer and the ILD layer.

5 . The method of claim 1 , further comprising:
forming an upper dielectric layer on the gate cap, the spacer, and the ILD layer; removing a portion of the upper dielectric layer and the ILD layer, selective to the gate cap and the spacer, to form a contact opening, the contact opening exposing an upper surface of a source-drain region; and forming an electrical contact in the contact opening.

6 . A method comprising:
forming a first embedded etch stop layer in a gate dielectric layer and a work-function metal layer of a replacement metal gate (RMG) using ion implantation, wherein the first embedded etch stop layer comprises a layer of dopant atoms embedded at a depth below an upper portion of the gate dielectric layer and an upper portion of the work-function metal layer; removing the upper portion of the gate dielectric layer and the upper portion of the work-function metal layer; removing the first embedded etch stop layer to expose a lower portion of the gate dielectric layer and a lower portion of the work-function metal layer; forming a gate electrode on the lower portion of the gate dielectric layer and the lower portion of the work-function metal layer; forming a second embedded etch stop layer in the gate electrode, wherein the second embedded etch stop layer comprises a layer of dopant atoms embedded at a depth below an upper portion of the gate electrode; removing the upper portion of the gate electrode; and forming a gate cap on the second embedded etch stop layer, the gate cap having an upper surface that is substantially flush with an upper surface of a spacer adjacent to the RMG and an upper surface of an ILD layer adjacent to the spacer.

7 . The method of claim 6 , further comprising:
forming an upper dielectric layer on the gate cap, the spacer, and the ILD layer; removing a portion of the upper dielectric layer and the ILD layer, selective to the gate cap and the spacer, to form a contact opening, the contact opening exposing an upper surface of a source-drain region; and forming an electrical contact in the contact opening.

8 . The method of claim 6 , wherein the dopant atoms comprise silicon, carbon, or nitrogen.

9 . The method of claim 6 , wherein the first embedded etch stop layer and the second embedded etch stop layer extend laterally through the spacer and the ILD layer.

10 . The method of claim 1 , wherein the work-function metal layer comprises one or more layers of metals having compositions of aluminum, lanthanum oxide, magnesium oxide, strontium titanate, tantalum carbide, titanium nitride, or strontium oxide.

11 . A method comprising:
removing a dummy gate from a field effect transistor (FET) structure to form a gate recess region, the FET structure comprising the dummy gate formed on a substrate, a spacer adjacent to the dummy gate, and a source-drain region adjacent to the spacer; forming a gate dielectric layer in the gate recess region, the gate dielectric layer having an upper surface that is substantially flush with an upper surface of the spacer; forming a work-function metal layer on the gate dielectric layer, the work-function metal layer having an upper surface that is substantially flush with an upper surface of the spacer; forming a first embedded etch stop layer in the gate dielectric layer and the work-function metal layer using ion implantation, wherein the first embedded etch stop layer comprises a layer of dopant atoms embedded at a depth below an upper portion of the gate dielectric layer and an upper portion of the work-function metal layer; removing the upper portion of the gate dielectric layer; removing the upper portion of the work-function metal layer; removing the first embedded etch stop layer to expose a lower portion of the gate dielectric layer and a lower portion of the work-function metal layer; forming a gate electrode on the lower portion of the gate dielectric layer and the lower portion of the work-function metal layer; and forming a gate cap in the gate recess region, the gate cap having an upper surface that is substantially flush with an upper surface of the spacer and an upper surface of an interlevel dielectric (ILD) layer adjacent to the spacer.

12 . The method of claim 11 , further comprising:
forming a second embedded etch stop layer in the gate electrode, wherein the second embedded etch stop layer comprises a layer of dopant atoms embedded at a depth below an upper portion of the gate electrode; and removing the upper portion of the gate electrode.

13 . The method of claim 12 , wherein the dopant atoms comprise silicon, carbon, or nitrogen.

14 . The method of claim 12 , wherein the second embedded etch stop layer extends laterally through the spacer and the ILD layer.

15 . The method of claim 11 , wherein the dopant atoms comprise silicon, carbon, or nitrogen.

16 . The method of claim 11 , further comprising:
forming an upper dielectric layer on the gate cap, the spacer, and the ILD layer; removing a portion of the upper dielectric layer and the ILD layer, selective to the gate cap and the spacer, to form a contact opening, the contact opening exposing an upper surface of a source-drain region; and forming an electrical contact in the contact opening.

17 . The method of claim 11 , wherein the first embedded etch stop layer extends laterally through the spacer and the ILD layer.

18 .- 20 . (canceled)

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cai Xiuyu
• Cheng Kangguo
• Khakifirooz Ali
• Xie Ruilong

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title