Method and system for implementing high-speed interfaces between semiconductor dies in optical communication systems

Patent metadata

Field	Value
Publication number	US-9772460-B2
Application number	US-201113033439-A
Country	US
Kind code	B2
Filing date	Feb 23, 2011
Priority date	Feb 23, 2010
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

First claim

What is claimed is:

1. A method for processing signals, the method comprising:
in an optical communication system, communicating electrical signals between an electronics die and an optoelectronics die via coupling pads on said electronics die and said optoelectronics die, wherein said coupling pads are located at low impedance points between two cascode transistors in one or more transmit paths and/or one or more receive paths in said optical communication system, wherein a first of said two cascode transistors is integrated in said electronics die and a second of said two cascode transistors is integrated in said optoelectronics die.

2. The method according to claim 1 , comprising communicating said electrical signals via one or more current-mode interfaces.

3. The method according to claim 2 , wherein said one or more current-mode interfaces comprise a cascode amplifier stage split between a source terminal of said first of said two cascode transistors integrated in said electronics die and a drain terminal of said second of said two cascode transistors integrated in said optoelectronics die.

4. The method according to claim 2 , wherein said one or more current-mode interfaces comprise a cascode amplifier stage split between a source terminal of said first of said two cascode transistors integrated in said optoelectronics die and a drain terminal of said second of said two cascode transistors integrated in said electronics die.

5. The method according to claim 1 , comprising communicating said electrical signals via one or more controlled-impedance interfaces.

6. The method according to claim 5 , wherein said one or more controlled-impedance interfaces comprise one or more transmission line drivers on a first die and one or more transmission lines on a second die of said optical communication system.

7. The method according to claim 1 , comprising communicating said electrical signals via one or more capacitively-coupled interfaces.

8. The method according to claim 7 , wherein said capacitively-coupled interfaces comprise capacitors formed by one or more of said contact pads on said electronics die and one or more of said contact pads on said optoelectronics die.

9. The method according to claim 1 , comprising communicating said electrical signals via one or more inductively-coupled interfaces.

10. The method according to claim 1 , wherein said coupling pads are connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin.

11. The method according to claim 1 , wherein said electronics die and said optoelectronics die are coupled in a flip-chip configuration.

12. The method according to claim 1 , wherein said electronics die comprises a complimentary metal-oxide-semiconductor (CMOS) die.

13. The method according to claim 1 , wherein said optoelectronics die comprises a CMOS die.

14. A system for processing signals, the system comprising:
an optical communication system comprising an electronics die and an optoelectronics die, said electronics die and said optoelectronics die comprising circuitry that is operable to communicate electrical signals between said electronics die and said optoelectronics die via coupling pads on said electronics die and said optoelectronics die, wherein said coupling pads are located at low impedance points between two cascode transistors in one or more transmit paths and/or one or more receive paths in said optical communication system, wherein a first of said two cascode transistors is integrated in said electronics die and a second of said two cascode transistors is integrated in said optoelectronics die.

15. The system according to claim 14 , wherein said circuitry is operable to communicate said electrical signals via one or more current-mode interfaces.

16. The system according to claim 15 , wherein said one or more current-mode interfaces comprise a cascode amplifier stage split between a source terminal of said first of said two cascode transistors integrated in said electronics die and a drain terminal of said second of said two cascode transistors integrated in said optoelectronics die.

17. The system according to claim 15 , wherein said one or more current-mode interfaces comprise a cascode amplifier stage split between a source terminal of said first of said two cascode transistors integrated in said optoelectronics die and a drain terminal of said second of said two cascode transistors integrated in said electronics die.

18. The system according to claim 14 , wherein said circuitry is operable to communicate said electrical signals via one or more controlled-impedance interfaces.

19. The system according to claim 18 , wherein said one or more controlled-impedance interfaces comprise one or more transmission line drivers on a first die and one or more transmission lines on a second die of said optical communication system.

20. The system according to claim 14 , wherein said circuitry is operable to communicate said electrical signals via one or more capacitively-coupled interfaces.

21. The system according to claim 20 , wherein said capacitively-coupled interfaces comprise capacitors formed by one or more of said contact pads on said electronics die and one or more of said contact pads on said optoelectronics die.

22. The system according to claim 14 , wherein said circuitry is operable to communicate said electrical signals via one or more inductively-coupled interfaces.

23. The system according to claim 14 , wherein said coupling pads are connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin.

24. The system according to claim 14 , wherein said electronics die and said optoelectronics die are coupled in a flip-chip configuration.

25. The system according to claim 14 , wherein said electronics die comprises a complimentary metal-oxide-semiconductor (CMOS) die.

26. The system according to claim 14 , wherein said optoelectronics die comprises a CMOS die.

Assignees

• Kucharski Daniel
• Guckenberger John Andrew
• Pinguet Thierry
• Abdalla Sherif
• Luxtera Inc

Inventors

• Kucharski Daniel
• Guckenberger John Andrew
• Pinguet Thierry
• Abdalla Sherif

Classifications

• G02B6/4286

  Optical modules with optical power monitoring · CPC title

• G02B6/4274 Primary

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title