Multi-stage equalization

Patent metadata

Field	Value
Publication number	US-9772378-B2
Application number	US-201414471726-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Aug 28, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An example apparatus for interfacing between automatic test equipment (ATE) and a device under test (DUT) includes: multiple stages arranged in sequence between the ATE and the DUT, where each of the multiple stages includes a driver, at least two of the multiple stages each includes a filter, each filter is arranged between two drivers, and each filter is configured to reduce jitter produced by a preceding driver in a signal transmitted between the ATE and the DUT.

First claim

What is claimed is:

1. An apparatus for interfacing between automatic test equipment (ATE) and a device under test (DUT), the apparatus comprising:
multiple stages arranged in sequence between the ATE and the DUT, each of the multiple stages comprising a driver, at least two of the multiple stages each comprising a filter, each filter being arranged between two drivers;
wherein a filter in a stage among the multiple stages is configured to reduce jitter produced by a preceding driver in the stage in a signal transmitted between the ATE and the DUT, the jitter reduced by the filter corresponding to a width of the signal at a predefined crossing point at a point on a path between the ATE and the DUT; and
wherein, reduction of jitter at each of the at least two of the multiple stages causes a reduction in overall jitter of the signal received by the DUT.

2. The apparatus of claim 1 , wherein a last of the multiple stages comprises a driver but not a filter between the driver and the DUT.

3. The apparatus of claim 1 , wherein a last of the multiple stages comprises a driver and a filter between the driver and the DUT.

4. The apparatus of claim 1 , wherein at least two of the filters have different configurations, the different configurations resulting from different corrections required for reduction of jitter.

5. The apparatus of claim 1 , wherein at least one of the filters comprises a high-pass compensation filter.

6. The apparatus of claim 1 , wherein at least one of the drivers comprises an AND gate or a splitter.

7. An apparatus for interfacing between automatic test equipment (ATE) and a device under test (DUT), the apparatus comprising:
a first stage comprising a first driver and a first filter, the first driver for receiving an initial signal based on an output of the ATE, the first driver for outputting a first output signal based on the initial signal, the first filter for receiving the first output signal from the first driver and for performing a first equalization on the first output signal to produce a first stage signal, the first equalization reducing jitter from the initial signal by affecting a width of the first output signal at a predefined crossing point at a point on a path between the ATE and the DUT;
a second stage comprising a second driver and a second filter, the second driver for receiving the first stage signal and for outputting a second output signal based on the first stage signal, the second filter for receiving the second output signal from the second driver and for performing a second equalization on the second output signal to produce a second stage signal, the second equalization reducing jitter from the first stage signal by affecting a width of the second output signal at a predefined crossing point at a point on the path between the ATE and the DUT; and
a third stage comprising a third driver, the third driver for receiving the second stage signal and for outputting a third output signal based on the second stage signal, the third output signal being output on a path to the DUT;
wherein reducing jitter from the initial signal and reducing jitter from the first stage signal reduces an overall amount of jitter in the third output signal.

8. The apparatus of claim 7 , wherein the third stage comprises a third filter on the path to the DUT, the third filter for receiving the third output signal from the third driver and for performing an equalization on the third output signal to produce a third stage signal; and
a fourth stage comprising a fourth driver, the fourth driver for receiving the third stage signal and for outputting a fourth output signal based on the third stage signal, the fourth output signal being output on a path to the DUT.

9. The apparatus of claim 8 , wherein the fourth stage comprises a fourth filter on the path to the DUT, the fourth filter for receiving the fourth output signal from the fourth driver and for performing an equalization on the fourth output signal to produce a fourth stage signal; and
a fifth stage comprising a fifth driver, the fifth driver for receiving the fourth stage signal and for outputting a fifth output signal based on the fourth stage signal, the fifth output signal being output on a path to the DUT.

10. The apparatus of claim 9 , wherein the fifth stage comprises a fifth filter between the fifth stage and the DUT, the fifth filter for receiving the fifth output signal from the fifth driver and for performing an equalization on the fifth output signal to produce a fifth stage signal that is provided to the DUT.

11. The apparatus of claim 9 , wherein the first filter is configured to correct for jitter produced by the first driver by reducing the width of the first output signal, the second filter is configured to correct for jitter produced by the second driver by reducing the width of the second output signal, the third filter is configured to correct for jitter produced by the third driver, and the fourth filter is configured to correct for jitter produced by the fourth driver; and
wherein at least two of the first driver, the second driver, the third driver, and the fourth driver have different configurations.

12. The apparatus of claim 9 , wherein there is no filter between the fifth driver and the DUT.

13. The apparatus of claim 7 , wherein there is no filter between the third driver and the DUT.

14. The apparatus of claim 7 , wherein the first filter is configured to correct for jitter produced by the first driver and the second filter is configured to correct for jitter produced by the second driver.

15. The apparatus of claim 7 , wherein at least one of the first filter and the second filter comprises a high-pass compensation filter.

16. The apparatus of claim 7 , wherein the first driver comprises an AND gate or a splitter, and the second driver comprises an AND gate or a splitter.

17. A test system comprising:
automatic test equipment (ATE) to output test signals to a device under test (DUT); and
an interface between the ATE and the DUT, the interface comprising stages, the stages comprising drivers arranged in sequence and filters arranged among the drivers, the stages to perform multi-stage equalization on test signals output from the ATE to the DUT, the multi-stage equalization comprising reducing jitter on a test signal among the test signals at each stage so as to reduce an overall jitter of the test signal, the jitter at each stage being reduced by affecting a width of the test signal at a predefined crossing point.

18. The test system of claim 17 , wherein the stages comprise:
multiple stages arranged in sequence between the ATE and the DUT, each of the multiple stages comprising a driver, at least two of the multiple stages each comprising a filter, each filter being arranged between two drivers;
wherein each filter is configured to reduce jitter produced by a preceding driver in the test signal.

19. The test system of claim 17 , wherein a last of the multiple stages comprises a driver but not a filter between the driver and the DUT; and
wherein at least two of the filters have different configurations, the different configurations resulting from different corrections required for reduction of jitter.

20. The test system of claim 17 , wherein a last of the multiple stages comprises a driver but not a filter between the driver and the DUT; and
wherein at least three of the filters have different configurations, the different configurations resulting from different corrections required for reduction of jitter.

Assignees

• Teradyne Inc

Inventors

• Lyons Timothy Daniel

Classifications

• G01R31/31924 Primary

  Voltage or current aspects, e.g. driver, receiver · CPC title

• G01R31/31905

  Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture · CPC title

• G01R35/00 Primary

  Testing or calibrating of apparatus covered by the other groups of this subclass · CPC title

• G01R31/2889

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title