Two dimensional shift array for image processor

Patent metadata

Field	Value
Publication number	US-9769356-B2
Application number	US-201514694750-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Apr 23, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.

First claim

The invention claimed is:

1. An apparatus, comprising:
an execution lane array coupled to a two dimensional shift register array structure, wherein, locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers, wherein, the two-dimensional shift register array structure couples locations along both horizontal and vertical axes so as to provide for shifting of two dimensional data arrays along both the horizontal and vertical axes such that data arrangement within the arrays remains intact for both horizontal shifts and vertical shifts, and wherein, a pair of logically neighboring locations in the two-dimensional shift register array structure have a physical array location between their respective physical locations.

2. The apparatus of claim 1 wherein the two-dimensional shift register array structure includes coupling between neighboring locations in the two-dimensional shift register array structure.

3. The apparatus of claim 2 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are two locations apart.

4. The apparatus of claim 2 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are at least one of three and four locations apart.

5. The apparatus of claim 1 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are at least one of two, three and four locations apart.

6. The apparatus of claim 1 wherein the dimensions of the two-dimensional shift register array structure are larger than the dimensions of the execution lane array such that a halo region exists outside the execution lane array.

7. The apparatus of claim 1 wherein a physical array structure of the two dimensional shift register array structure imposes a toroid structure.

8. The apparatus of claim 6 wherein the two-dimensional shift register array structure couples a last logical location to a first logical location to support a roll operation.

9. The apparatus of claim 6 wherein the two-dimensional shift register array structure is coupled to a random access memory by way of a swizzled data bus.

10. A computing system, comprising:
a plurality of processing cores;
a memory controller coupled to the plurality of processing cores, the memory controller coupled to a system memory;
an image processor, the image processor including an execution lane array coupled to a two dimensional shift register array structure, wherein, locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers, wherein, the two-dimensional shift register array structure couples locations along both horizontal and vertical axes so as to provide for shifting of two dimensional data arrays along both the horizontal and vertical axes such that data arrangement within the arrays remains intact for both horizontal shifts and vertical shifts, and wherein, a pair of logically neighboring locations in the two-dimensional shift register array structure have a physical array location between their respective physical locations.

11. The computing system of claim 10 wherein the two-dimensional shift register array structure includes coupling between neighboring locations in the two-dimensional shift register array structure.

12. The computing system of claim 11 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are two locations apart.

13. The computing system of claim 11 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are at least one of three and four locations apart.

14. The computing system of claim 10 wherein the two-dimensional shift register array structure includes coupling between locations in the two-dimensional shift register array structure that are at least one of two, three and four locations apart.

15. The computing system of claim 10 wherein the dimensions of the two-dimensional shift register array structure are larger than the dimensions of the execution lane array such that a halo region exists outside the execution lane array.

16. The computing system of claim 10 wherein a physical array structure of the two dimensional shift register array structure imposes a toroid structure.

17. The computing system of claim 15 wherein the two-dimensional shift register array structure couples a last logical location to a first logical location to support a roll operation.

18. The computing system of claim 15 wherein the two-dimensional shift register array structure is coupled to a random access memory by way of a swizzled data bus.

19. A method, comprising:
shifting, in a same direction and number of locations, a first two dimensional data array along a horizontal axis from multiple contiguous locations within a two-dimensional shift register array structure to provide each of multiple different execution lanes within an execution lane array a new value within respective dedicated registers of the multiple different execution lanes and such that data arrangement within the first two dimensional data array remains intact, the different execution lanes coupled to their respective dedicated registers at same respective locations of the execution lane array and the two-dimensional shift register array structure; and,
shifting, in a same direction and number of locations, a second two dimensional data array along a vertical axis from multiple contiguous locations within the two-dimensional shift register array structure to provide each of multiple different execution lanes within the execution lane array a new value within respective dedicated registers of the multiple different execution lanes and such that data arrangement within the second two dimensional data array remains intact
wherein physical shift amounts of the shiftings are different than logical shift amounts of the shiftings.

20. The method of claim 19 wherein the distance of at least one of the shiftings is one logical location.

21. The method of claim 19 wherein the distance is any of two, three, four logical locations.

22. The method of claim 19 further comprising performing a roll of data within the two-dimensional register array structure.

23. A non-transitory computer readable storage medium containing program code for compilation and loading of a formatted description of an electronic circuit for fabrication into a semiconductor chip thereby causing the semiconductor chip to operate as the electronic circuit, the electronic circuit comprising:
an execution lane array coupled to a two dimensional shift register array structure, wherein, locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers, wherein, the two-dimensional shift register array structure couples locations along both horizontal and vertical axes so as to provide for shifting of two dimensional d

Assignees

• Google Inc

Inventors

• Shacham Ofer
• Redgrave Jason Rupert
• Meixner Albert
• Zhu Qiuling
• Finchelstein Daniel Frederic
• Patterson David
• Stark Donald

Classifications

• G06F9/3004

  to perform operations on memory · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• H04N5/14

  Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00) · CPC title