RF-DC power converter

Patent metadata

Field	Value
Publication number	US-9768711-B2
Application number	US-201514740021-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Jun 13, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A rectifier comprising a chain of transistors for RF-DC conversion. In order to compensate for the thresholds of the transistors, each transistor can be connected to a junction earlier or later in the chain. By using both p-type and n-type transistors in the same chain, the different types of transistors can be compensated in different directions allowing more transistors to be compensated. Additional transistors connected to the gates of transistors of the main chain can allow the transistors of the main chain to be forward compensated at one part of the input cycle and backward compensated in another part to minimize both the voltage threshold of the rectifier and the leakage current. The line for compensation of the voltage threshold during forward conduction can comprise a solid line or a transistor, and if a transistor is used it may be diode-connected.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A power conversion circuit comprising:
a first input line and a second input line, the first and second input lines configured to receive an alternating voltage differential between the first and second input lines;
a multi-stage rectifier comprising n transistors arranged in series, where n is at least 2, each transistor having a gate, a source and a drain, adjacent transistors of the series being connected so that for adjacent p-type transistors, one of them being left p-type transistor positioned at the left-hand side and the other being right p-type transistor positioned at the right-hand side, the drain of the left p-type transistor is connected to the source of the right p-type transistor and source of the right p-type transistor is connected to the drain of the left p-type transistor, for adjacent n-type transistors, one of them being left n-type transistor positioned at the left-hand side and the other being right n-type transistor positioned at the right-hand side, the source of the left n-type transistor is connected to the drain of the right n-type transistor and drain of the right n-type transistor is connected to the source of the left n-type transistor, for a p-type transistor adjacent to an n-type transistor, n-type transistor positioned at the left-hand side and the p-type transistor positioned at the right-hand side, the source of the p-type transistor is connected to the source of the n-type transistor and drain of the p-type transistor is connected to the drain of the n-type transistor to form a junction, each junction being connected to one of the first input line and the second input line via a capacitor, with adjacent junctions having one junction of the adjacent junctions connected to the first input line and the other junction of the adjacent junctions connected to the second input line;
the gate of a k th transistor of the multi-stage rectifier, where k is a number between 1 and n, is connected to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor for the p-type transistor or to the source of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor for the n-type transistor, at least one of the transistor in the multi-stage rectifier being p-type and at least one being n-type.

2. The power conversion circuit of claim 1 further comprising an auxiliary chain of n p-type transistors, each auxiliary transistor having a gate, a source and a drain, each transistor of the auxiliary chain being connected to a p-type transistor of the multi-stage rectifier in the main chain, so that the gate of the k th main auxiliary transistor, where k is a number between 1 and n, is connected to the source of the k th main transistor, the source of the k th auxiliary transistor is connected to the gate of the k th main transistor and also connected to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor, and the drain of the k th auxiliary transistor is connected to the drain of the k th main transistor or the drain of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor.

3. The power conversion circuit of claim 2 further comprising a diode connected transistor on a line connecting the gate of the k th main transistor to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor.

4. The power conversion circuit of claim 1 further comprising an auxiliary chain of n n-type transistors, each auxiliary transistor having a gate, a source and a drain, each transistor of the auxiliary chain being connected to an n-type transistor of the multi-stage rectifier in the main chain, so that the gate of the k th auxiliary transistor, where k is a number between 1 and n, is connected to the source of the k th main transistor, the source of the k th auxiliary transistor is connected to the gate of the k th main transistor and also connected to the source of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor, and the drain of the k th auxiliary transistor is connected to the drain of the k th main transistor or to the drain of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor.

5. The power conversion circuit of claim 4 further comprising a diode connected transistor on a line connecting the gate of the k th main transistor to the source of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor.

6. The power conversion circuit of claim 1 further comprising an additional transistor connected in series with the multistage rectifier, the additional transistor having a gate, a source and a drain, the gate of the additional transistor being connected to the drain of the additional transistor.

7. The power conversion circuit of claim 1 in which the gate of the k th transistor is connected to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st transistor for p-type transistor and to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor for n-type transistor.

8. The power conversion circuit of claim 7 in which N of the transistors in the multistage rectifier arranged in series are n-type and all but N of the transistors in multistage rectifier arranged in series are p-type.

9. The power conversion circuit of claim 1 in which the second input line is grounded.

10. The power conversion circuit of claim 1 in which the body terminal of each p-type transistor is connected to the respective drain and the body terminal of each n-type transistor is either grounded or connected to the respective drain terminal.

11. A power conversion circuit comprising:
an auxiliary chain of n auxiliary transistors, where n is at least 2, each auxiliary transistor having a gate, a source and a drain; a main chain of n main transistors connected in series, each main transistor having a gate, a source and a drain; each transistor of the auxiliary being connected to a respective transistor of the main chain of multi-stage rectifier;
wherein, if the auxiliary and main transistors are n-type, the gate of a k th auxiliary transistor, where k is a number between 1 and n, is connected to the source of the k th main transistor, the source of the k th auxiliary transistor is connected to the gate of the k th main transistor, the source of the k th auxiliary transistor is also connected to the source of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor, and the drain of the k th auxiliary transistor is connected to the drain of the k th main transistor;
and
wherein, if the auxiliary and main transistors are p-type, the gate of a k th auxiliary transistor is connected to the source of the k th main transistor, the source of k th auxiliary transistor is connected to the gate of the k th main transistor, the source of the k th auxiliary transistor is also connected to the source of the (k−1) th , or the (k−2) th , . . . , or the 1 st main transistor, and the drain of the k th auxiliary transistor is connected to the drain of the k th main transistor.

12. The power conversion circuit of claim 11 in which the transistors of the main chain and auxiliary chain are n-type and further comprising a p-type transistor on a line connecting the gate of the k th main transistor to the source of the (k+1) th , or the (k+2) th , . . . , or the n th main transistor, such that the gate of the additional p-type auxiliary transistor is connected to the gate of the k th n-type auxiliary transistor, and the source of the additional p-type auxiliary transistor is connected to the source

Assignees

• Univ Alberta

Inventors

• Hameed Zohaib
• Moez Kambiz

Classifications

• H02M7/25 Primary

  arranged for operation in series, e.g. for multiplication of voltage · CPC title

• H02M7/103

  Containing passive elements (capacitively coupled) which are ordered in cascade on one source · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title