Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof

Patent metadata

Field	Value
Publication number	US-9768323-B2
Application number	US-201715455082-A
Country	US
Kind code	B2
Filing date	Mar 9, 2017
Priority date	Apr 14, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A dual gate oxide semiconductor TFT substrate is made by utilizing a halftone mask to implement one photo process, which accomplishes patterning of an oxide semiconductor layer and forms an oxide conductor layer with ion doping process. Patterning of a bottom gate isolation layer and a top gate isolation layer are performed at the same time with one photo process. A first top gate, a first source, a first drain, a second top gate, a second source, and a second drain are formed at the same time with one photo process. Patterning of a flat layer, a passivation layer, and a top gate isolation layer are performed at the same time with one photo process. As such, the number of photo processes applied to manufacture the TFT substrate is reduced to five and the manufacturing process is shortened to thereby raise the production efficiency and lower the production cost.

First claim

What is claimed is:

1. A structure of a dual gate oxide semiconductor thin-film transistor (TFT) substrate, comprising a substrate, a first bottom gate and a second bottom gate positioned on the substrate, a bottom gate isolation layer positioned on the substrate and the first bottom gate and the second bottom gate, a first oxide semiconductor layer positioned on the bottom gate isolation layer above the first bottom gate, a second oxide semiconductor layer positioned on the bottom gate isolation layer above the second bottom gate, an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first bottom gate away from the second bottom gate, a top gate isolation layer positioned on the first oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductor layer and the bottom gate isolation layer, a first top gate positioned on the top gate isolation layer above the first oxide semiconductor layer, a first source and a first drain positioned on the top gate isolation layer respectively at two sides of the first top gate, a second top gate positioned on the top gate isolation layer above the second oxide semiconductor layer, a second source and a second drain positioned on the top gate isolation layer respectively at two sides of the second top gate, a passivation layer positioned on the first top gate, the first source, the first drain, the second top gate, the second source, the second drain and the top gate isolation layer, and a flat layer positioned on the passivation layer;
wherein two areas of the first oxide semiconductor layer and two areas of the second oxide semiconductor layer are ion doping conductor layers; the top gate isolation layer is provided with first via holes correspondingly above the two side areas of the first oxide semiconductor layer, and the top gate isolation layer is provided with second via holes correspondingly above the two side areas of the second oxide semiconductor layer, and the top gate isolation layer is provided with a third via hole correspondingly above the oxide conductor layer; the bottom gate isolation layer and the top gate isolation layer are provided with a fourth via hole correspondingly between the first bottom gate and the second bottom gate; the top gate isolation layer, the passivation layer and the flat layer are provided with a fifth via hole correspondingly above the oxide conductor layer;
wherein the first source and the first drain respectively contact with the two side areas of the first oxide semiconductor layer through the first via holes; the second source and the second drain respectively contact with the two side areas of the second oxide semiconductor layer through the second via holes; the first source contacts with the oxide conductor layer through the third via hole; the second source contacts with the first bottom gate through the fourth via hole; the fifth via hole exposes a portion of the oxide conductor layer; and
wherein the first bottom gate, the first oxide semiconductor layer, the first source, the first drain and the first top gate construct a first dual gate TFT, and the second bottom gate, the second oxide semiconductor layer, the second source, the second drain and the second top gate construct a second dual gate TFT; the oxide conductor layer constructs an anode of an organic light emitting display (OLED).

2. The structure of the dual gate oxide semiconductor TFT substrate according to claim 1 , wherein materials of the first oxide semiconductor layer and the second oxide semiconductor layer are indium gallium zinc oxide (IGZO), and the oxide conductor layer is manufactured by implementing ion doping to the IGZO semiconductor layer.

3. The structure of the dual gate oxide semiconductor TFT substrate according to claim 1 , wherein a material of the flat layer is organic photoresist; materials of the bottom gate isolation layer and the top gate isolation layer are silicon nitride, silicon oxide, or a combination of the two; materials of the first bottom gate, the first top gate, the first source, the first drain, the second bottom gate, the second top gate, the second source and the second drain are a stacked combination of one or more of molybdenum, titanium, aluminum and copper.

4. A structure of a dual gate oxide semiconductor thin film transistor (TFT) substrate, comprising a substrate, a first bottom gate and a second bottom gate positioned on the substrate, a bottom gate isolation layer positioned on the substrate and the first bottom gate and the second bottom gate, a first oxide semiconductor layer positioned on the bottom gate isolation layer above the first bottom gate, a second oxide semiconductor layer positioned on the bottom gate isolation layer above the second bottom gate, an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first bottom gate away from the second bottom gate, a top gate isolation layer positioned on the first oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductor layer and the bottom gate isolation layer, a first top gate positioned on the top gate isolation layer above the first oxide semiconductor layer, a first source and a first drain positioned on the top gate isolation layer respectively at two sides of the first top gate, a second top gate positioned on the top gate isolation layer above the second oxide semiconductor layer, a second source and a second drain positioned on the top gate isolation layer respectively at two sides of the second top gate, a passivation layer positioned on the first top gate, the first source, the first drain, the second top gate, the second source, the second drain and the top gate isolation layer, and a flat layer positioned on the passivation layer;
wherein two areas of the first oxide semiconductor layer and two areas of the second oxide semiconductor layer are ion doping conductor layers; the top gate isolation layer is provided with first via holes correspondingly above the two side areas of the first oxide semiconductor layer, and the top gate isolation layer is provided with second via holes correspondingly above the two side areas of the second oxide semiconductor layer, and the top gate isolation layer is provided with a third via hole correspondingly above the oxide conductor layer; the bottom gate isolation layer and the top gate isolation layer are provided with a fourth via hole correspondingly between the first bottom gate and the second bottom gate; the top gate isolation layer, the passivation layer and the flat layer are provided with a fifth via hole correspondingly above the oxide conductor layer;
wherein the first source and the first drain respectively contact with the two side areas of the first oxide semiconductor layer through the first via holes; the second source and the second drain respectively contact with the two side areas of the second oxide semiconductor layer through the second via holes; the first source contacts with the oxide conductor layer through the third via hole; the second source contacts with the first bottom gate through the fourth via hole; the fifth via hole exposes a portion of the oxide conductor layer;
wherein the first bottom gate, the first oxide semiconductor layer, the first source, the first drain and the first top gate construct a first dual gate TFT, and the second bottom gate, the second oxide semiconductor layer, the second source, the second drain and the second top gate construct a second dual gate TFT; the oxide conductor layer constructs an anode of an organic light emitting display (OLED);
wherein materials of the first oxide semiconductor layer and the second oxide semiconductor layer are indium gallium zinc oxide (IGZO), and the oxide conductor layer is manufactured by implementing ion doping to the IGZO semiconductor layer;
wherein

Assignees

• Shenzhen China Star Optoelect

Inventors

• Ge Shimin
• Zhang Hejing
• Tseng Chihyuan
• Su Chihyu
• Li Wenhui
• Shi Longqiang
• Lv Xiaowen

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title