Metal oxide thin film transistor and manufacturing method thereof, display substrate and display device
US-2017092660-A1 · Mar 30, 2017 · US
Metal oxide TFT with improved source/drain contacts and reliability
US9768322B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9768322-B2 |
| Application number | US-201615225592-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 1, 2016 |
| Priority date | Jun 8, 2011 |
| Publication date | Sep 19, 2017 |
| Grant date | Sep 19, 2017 |
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Abstract
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A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.
First claim
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Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is: 1. A stable metal oxide semiconductor thin film transistor with ohmic source/drain contacts and high reliability comprising: a substrate with a gate, a layer of gate insulator adjacent the gate, and a layer of metal oxide semiconductor material positioned on the layer of gate insulator opposite the gate; and, a…
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- What does patent US9768322B2 cover?
- A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase th…
- Who is the assignee on this patent?
- Yu Gang, Shieh Chan-Long, Xiao Tian, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7869. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).