Gradient ternary or quaternary multiple-gate transistor

Patent metadata

Field	Value
Publication number	US-9768305-B2
Application number	US-61606809-A
Country	US
Kind code	B2
Filing date	Nov 10, 2009
Priority date	May 29, 2009
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a semiconductor substrate;
a insulation layer over the semiconductor substrate; and
epitaxy layers over the semiconductor substrate, the epitaxy layers having at least a portion extending through the insulation layer, wherein the epitaxy layers comprise a first III-V compound semiconductor material, and wherein the epitaxy layers further comprise:
a first layer, wherein the first layer is entirely disposed beneath a top surface of the insulation layer, wherein the first layer and the semiconductor substrate have a first lattice mismatch; and
a second layer over the first layer, wherein an uppermost surface of the second layer extends above the top surface of the insulation layer, wherein the second layer and the semiconductor substrate have a lattice mismatch different from the first lattice mismatch.

2. The integrated circuit structure of claim 1 , wherein the epitaxy layers further comprises a portion having continuously changed lattice constants.

3. The integrated circuit structure of claim 1 , wherein the epitaxy layers further comprise at least three layers, with lattice constant mismatches between the at least three layers and the semiconductor substrate increasing from lower ones of the at least three layers to upper ones of the at least three layers.

4. The integrated circuit structure of claim 1 , wherein the second layer forms a fin, and wherein sidewalls of the fin are vertically aligned to sidewalls of a portion of epitaxy layers lower than the top surface of the insulation layer.

5. The integrated circuit structure of claim 4 further comprising a high-bandgap epitaxy layer on sidewalls of the fin, wherein the high-bandgap epitaxy layer has a second bandgap greater than a first bandgap of the fin.

6. The integrated circuit structure of claim 5 , wherein the fin comprises InGaAs, and wherein the high-bandgap epitaxy layer comprises GaAs.

7. The integrated circuit structure of claim 5 , wherein the second bandgap is greater than the first bandgap by more than about 0.1 eV.

8. The integrated circuit structure of claim 1 , wherein the semiconductor substrate comprises silicon, wherein the epitaxy layers comprise an InGaAs layer, and wherein indium percentages increase from lower portions of the InGaAs layer to upper portions of the InGaAs layer.

9. The integrated circuit structure of claim 8 further comprising a GaAs layer under the lower portions of the InGaAs layer and contacting the semiconductor substrate.

10. The integrated circuit structure of claim 8 further comprising a germanium layer under the lower portions of the InGaAs layer and contacting the semiconductor substrate.

11. The integrated circuit structure of claim 1 , wherein the insulation layer comprises shallow-trench isolation (STI) regions.

12. An integrated circuit structure comprising:
a semiconductor substrate;
a insulation layer over the semiconductor substrate;
a fin extending from the semiconductor substrate, the fin extending through and above the insulation layer, the fin comprising a first III-V compound semiconductor material, the fin comprising:
a first layer having a first lattice constant; and
a second layer over the first layer, the second layer having a second lattice constant, the first lattice constant being different than the second lattice constant; and

a gate electrode extending over and along sidewalls of the second layer; and
a semiconductor layer interposed between the gate electrode and the second layer, the semiconductor layer comprising a different material than the second layer.

13. The integrated circuit structure of claim 12 , wherein the fin further comprises a third layer over the second layer, with lattice constant mismatches between the semiconductor substrate and the first layer, the second layer, and the third layer increasing from the first layer to the third layer.

14. The integrated circuit structure of claim 12 , wherein the first lattice constant is smaller than the second lattice constant.

15. The integrated circuit structure of claim 12 , wherein the second layer comprises a first material layer and a second material layer, the first material layer being interposed between the second material layer and the first layer, the first material layer and the second material layer being formed of same elements, the first material layer and the second material layer having different percentages of at least two of the elements.

16. The integrated circuit structure of claim 15 , wherein the first material layer and the second material layer comprise indium, gallium, and arsenic, the first material layer having a lower percentage of indium than the second material layer.

17. An integrated circuit structure comprising:
a semiconductor substrate;
a insulation layer over the semiconductor substrate;
a fin over the semiconductor substrate, the insulation layer extending along opposing sidewalls of the fin, the fin comprising a first III-V compound semiconductor material, the fin comprising:
a first layer, the first layer and the semiconductor substrate having a first lattice mismatch; and
a second layer over the first layer, the second layer and the semiconductor substrate have a second lattice mismatch, the first lattice mismatch being different than the second lattice mismatch; and

a gate electrode extending over and along sidewalls of the fin.

18. The integrated circuit structure of claim 17 , further comprising a high-bandgap epitaxy layer on sidewalls of the fin, wherein the high-bandgap epitaxy layer has a second bandgap greater than a first bandgap of the fin.

19. The integrated circuit structure of claim 17 , wherein the first layer comprises a GaAs layer.

20. The integrated circuit structure of claim 19 , wherein the second layer comprises a first InGaAs layer and a second InGaAs layer over the first InGaAs layer, wherein the first InGaAs layer has a lower percentage of indium than the second InGaAs layer.

Assignees

• Ko Chih-Hsin
• Wann Clement Hsingjen
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10D30/6211 Primary

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic