Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity

Patent metadata

Field	Value
Publication number	US-9768272-B2
Application number	US-201514870936-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall image transfer technique is provided. In the present application, the source/drain region (i.e., area) are defined by a mandrel structure, while the area for the functional gate structure are defined by the distance between spacers that are located on a pair of neighboring mandrel structures. The gate spacer is defined by the spacer present on the mandrel structures. In some embodiments, semiconductor fin erosion due to gate and gate spacer formation can be reduced or even eliminated.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, said method comprising:
forming a pair of spaced apart mandrel structures on a surface of an upper hard mask layer, said upper hard mask layer is located on a lower hard mask layer that is located above and surrounding a portion of a semiconductor fin, wherein a spacer is present on each sidewall surface of each mandrel structure, said forming said pair of mandrel structures comprises forming said lower hard mask layer, forming said upper hard mask layer on said lower hard mask layer, forming a layer of mandrel material, and patterning said layer of mandrel material;
etching said upper and lower hard mask layers utilizing each mandrel structure and said spacers an etch mask;
removing each mandrel structure to provide a pair of source/drain openings;
extending a length of each source/drain opening by etching through remaining portions of said upper hard mask layer and said lower hard mask layer to provide a pair of spaced apart upper hard mask spacer portions and a pair of lower hard mask spacer portions and to provide an extended length source/drain opening that exposes a surface of said semiconductor fin;
forming a doped epitaxial semiconductor material on said semiconductor fin and within each extended length source/drain opening;
forming a flowable dielectric material structure in a lower portion of each extended length source/drain opening and atop the epitaxial doped semiconductor material, said flowable dielectric material structure having a topmost surface that is coplanar with a topmost surface of each lower hard mask spacer portion; and
forming a functional gate structure contacting a sidewall surface of each lower hard mask spacer portion.

2. The method of claim 1 , wherein said semiconductor fin is formed by patterning an upper semiconductor material portion of a semiconductor substrate.

3. The method of claim 2 , wherein after said patterning a local isolation structure is formed at a footprint of said semiconductor fin.

4. The method of claim 1 , wherein said patterning said layer of mandrel material comprises:
forming a layer of hard mask material on said layer of mandrel material;
forming an optical planarization layer (OPL) on said layer of hard mask material;
forming an anti-reflective coating (ARC) on said OPL;
forming a photoresist material on said ARC;
patterning said photoresist material to provide a pair of spaced apart photoresist structures; and
etching through said ARC, said OPL, said layer of hard mask material and said layer of mandrel material utilizing said pair of spaced apart photoresist structures as an etch mask.

5. The method of claim 1 , wherein said spacers are formed by deposition of a spacer material and etching said spacer material.

6. The method of claim 1 , wherein said etching said upper and lower hard mask layers comprises at least one anisotropic etching process.

7. The method of claim 1 , further comprising forming a sacrificial material on sidewall surfaces of said spacers and said remaining portions of said upper and lower hard mask layers, said forming said sacrificial material is performed after said etching said upper and lower hard mask layers utilizing each mandrel structure and said spacers an etch mask and prior to said removing each mandrel structure.

8. The method of claim 7 , wherein said sacrificial material is removed after said forming said flowable dielectric material structure and prior to said forming said functional gate structure.

9. The method of claim 1 , wherein said forming said doped epitaxial semiconductor material comprises an epitaxial growth process.

10. The method of claim 1 , wherein said forming said flowable dielectric material structure comprises:
forming a flowable dielectric material; and
planarizing said flowable dielectric material.

11. The method of claim 10 , wherein said planarizing removes each upper hard mask spacer portion from atop each lower hard mask spacer portion.

12. The method of claim 1 , wherein said spacers are removed after said etching through remaining portions of said upper hard mask layer and said lower hard mask layer, and prior to said forming said flowable dielectric material structure.

13. A method of forming a semiconductor structure, said method comprising:
forming a pair of spaced apart mandrel structures on a surface of an upper hard mask layer, said upper hard mask layer is located on a lower hard mask layer that is located above and surrounding a portion of a semiconductor fin, wherein a spacer is present on each sidewall surface of each mandrel structure;
etching said upper and lower hard mask layers utilizing each mandrel structure and said spacers an etch mask;
removing each mandrel structure to provide a pair of source/drain openings;
extending a length of each source/drain opening by etching through remaining portions of said upper hard mask layer and said lower hard mask layer to provide a pair of spaced apart upper hard mask spacer portions and a pair of lower hard mask spacer portions and to provide an extended length source/drain opening that exposes a surface of said semiconductor fin;
forming a doped epitaxial semiconductor material on said semiconductor fin and within each extended length source/drain opening;
forming a flowable dielectric material structure in a lower portion of each extended length source/drain opening and atop the epitaxial doped semiconductor material, said flowable dielectric material structure having a topmost surface that is coplanar with a topmost surface of each lower hard mask spacer portion;
forming a functional gate structure contacting a sidewall surface of each lower hard mask spacer portion; and
forming a sacrificial material on sidewall surfaces of said spacers and said remaining portions of said upper and lower hard mask layers, said forming said sacrificial material is performed after said etching said upper and lower hard mask layers utilizing each mandrel structure and said spacers an etch mask and prior to said removing each mandrel structure.

14. A method of forming a semiconductor structure, said method comprising:
forming a pair of spaced apart mandrel structures on a surface of an upper hard mask layer, said upper hard mask layer is located on a lower hard mask layer that is located above and surrounding a portion of a semiconductor fin, wherein a spacer is present on each sidewall surface of each mandrel structure;
etching said upper and lower hard mask layers utilizing each mandrel structure and said spacers an etch mask;
removing each mandrel structure to provide a pair of source/drain openings;
extending a length of each source/drain opening by etching through remaining portions of said upper hard mask layer and said lower hard mask layer to provide a pair of spaced apart upper hard mask spacer portions and a pair of lower hard mask spacer portions and to provide an extended length source/drain opening that exposes a surface of said semiconductor fin;
forming a doped epitaxial semiconductor material on said semiconductor fin and within each extended length source/drain opening;
forming a flowable dielectric material structure in a lower portion of each extended length source/drain opening and atop the epitaxial doped semiconductor material, said flowable dielectric material structure having a topmost surface that is coplanar with a topmost surface of each lower hard mask spacer portion; and
forming a functional gate structure contacting a sidewall surface of each lower hard mask spacer portion, wherein said spacers are removed after said etching through remaining portio

Assignees

• IBM

Inventors

• Hashemi Pouya
• He Hong
• Reznicek Alexander
• Yamashita Tenko

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L21/3081

  Electricity · mapped topic