Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

US9768251B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9768251-B2
Application numberUS-201514947632-A
CountryUS
Kind codeB2
Filing dateNov 20, 2015
Priority dateNov 28, 2014
Publication dateSep 19, 2017
Grant dateSep 19, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a semiconductor structure comprising: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being encapsulated by a further dielectric material, thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semiconductor material in the cavity; forming an opening in the further dielectric material, laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material. 2. The method of claim 1 , wherein laterally removing the second semiconductor material comprises: forming an elongated structure of the second semiconductor material along a lateral wall of the cavity, and forming a flat lateral surface at the elongated structure. 3. The method of claim 2 , wherein laterally removing the second semiconductor material comprises: selectively etching the second semiconductor material without etching the dielectric layer and/or the further dielectric material. 4. The method of claim 1 , wherein recrystallizing the second semiconductor material sets in at an interface between the substrate and the second semiconductor material inside the opening in the dielectric layer. 5. The method of claim 1 , wherein the flat lateral surface at the elongated structure is a seed for growing the third semiconductor material as a crystalline material. 6. The method of claim 1 , wherein forming the third semiconductor material comprises a vapour epitaxial process. 7. The method of claim 1 , wherein melting the second semiconductor material comprises: heating above a melting point of the second semiconductor material for a predetermined time, and wherein recrystallizing comprises cooling the second semiconductor material below the melting point of the second semiconductor material. 8. The method of claim 1 , wherein the dielectric layer comprises the further dielectric material. 9. The method of claim 1 comprising: forming a further semiconductor material on a lateral surface of the third semiconductor material. 10. The method according to claim 9 , comprising: forming another layer of the third semiconductor material on the further semiconductor material, selectively removing the further semiconductor material and/or the second semiconductor material. 11. The method of claim 1 , wherein the second and/or the third and/or the further semiconductor material comprises germanium and/or a compound semiconductor material including a III-V compound semiconductor material, a II-VI compound semiconductor material, a IV-VI compound semiconductor material, a II-V compound semiconductor material, and/or a IV-IV compound semiconductor material. 12. A semiconductor structure formed by the method of claim 1 .

Assignees

Inventors

Classifications

  • Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

  • Arsenides · CPC title

  • Phosphides · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • Lateral overgrowth · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9768251B2 cover?
A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material be…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P14/2905. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).