Cell layout for SRAM FinFET transistors

Patent metadata

Field	Value
Publication number	US-9425201-B2
Application number	US-201514671568-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Nov 14, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

First claim

What is claimed is:

1. An SRAM cell array comprising:
a plurality of SRAM cells, each SRAM cell comprising six FinFETs including two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors;
wherein each PU transistor includes one active fin having a first fin width, the one active fin of each PU transistor being adjacent to each other;
wherein each PG transistor shares at least one active fin with a PD transistor;
wherein the at least one active fin shared by a PG transistor and a PD transistor has a second fin width smaller than the first fin width; and
wherein no dummy fin is disposed between the one active fin of each PU transistor in a memory cell, a dummy fin is disposed between a PU transistor and the at least one active fin shared by a PG transistor and the PD transistor, and at least one dummy fin is disposed between the at least one active fin shared by the PG transistor and PD transistor in the memory cell and a fin shared by a PG transistor and a PD transistor in an adjacent memory cells.

2. The SRAM cell array of claim 1 , wherein a ratio of second fin width over the first fin width is between about 0.6 and about 0.9.

3. The SRAM cell array of claim 1 , wherein a distance between active fins of the adjacent PU transistors is smaller than a distance between an active fin of a PU transistor and an active fin of a nearest PG or PD transistor.

4. The SRAM cell array of claim 1 , further comprising shortened dummy fins embedded in a shallow trench isolation (STI) layer below gates of the FinFETs.

5. The SRAM cell array of claim 4 , wherein the shortened dummy fins are disposed between the PU transistor and the at least one active fin shared by a PG and a PD transistor and between adjacent memory cells.

6. The SRAM cell array of claim 1 , wherein the PG and PD transistors include more than one active fin.

7. The SRAM cell array of claim 1 , wherein PU transistor active fins are curved.

8. The SRAM cell array of claim 7 , wherein a minimum angle between a gate electrode and the PU transistor active fins is 35 degrees.

9. An SRAM cell array, each cell comprising:
a first fin electrically coupled as a source/drain of a first pass-gate transistor and a source/drain of a first pull-down transistor;
a second fin electrically coupled as a source/drain of a first pull-up transistor;
a third fin electrically coupled as a source/drain of a second pull-up transistor; and
a fourth fin electrically coupled as a source/drain of a second pass-gate transistor and a source/drain of a second pull-down transistor;
wherein the second fin and the third fin are interposed between the first fin and the fourth fin; and
wherein a first distance between the first fin and a closest fin of the second fin and the third fin is greater than a second distance between the second fin and the third fin.

10. The SRAM cell array of claim 9 , further comprising one or more dummy fins, the one or more dummy fins having a fin height less than a fin height of the first fin, the second fin, the third fin, and the fourth fin.

11. The SRAM cell array of claim 10 , wherein a first dummy fin is interposed between the first fin and a closest fin of the second fin and the third fin, and wherein a second dummy fin is interposed between the fourth fin and a closest fin of the second fin and the third fin.

12. The SRAM cell array of claim 9 , wherein a fin width of second fin and the third fin is greater than a fin width of the first fin and the fourth fin.

13. The SRAM cell array of claim 9 , wherein at least one of the second fin and the third fin are curved.

14. The SRAM cell array of claim 9 , wherein the first fin comprises a plurality of fins.

15. The SRAM cell array of claim 14 , wherein the fourth fin comprises a plurality of fins.

16. An SRAM cell array, each cell comprising:
a first pass-gate transistor and a first pull-down transistor sharing a first fin;
a first pull-up transistor including a second fin;
a second pull-up transistor including a third fin; and
a second pass-gate transistor and a second pull-down transistor sharing a fourth fin;
wherein the second fin and the third fin are interposed between the first fin and the fourth fin;
wherein the first fin has a first ratio of a first fin top width to a first fin bottom width;
wherein the second fin has a second ratio of a second fin top width to a second fin bottom width; and
wherein the first ratio is greater than the second ratio.

17. The SRAM cell array of claim 16 , wherein a distance between the first fin and an adjacent fin of the second fin and the third fin is greater than a distance between the second fin and the third fin.

18. The SRAM cell array of claim 16 , wherein the first fin comprises a plurality of fins.

19. The SRAM cell array of claim 16 , wherein a distance between the first fin of a first cell and the first fin of a second cell is less than a distance between the second fin and the third fin of a same cell.

20. The SRAM cell array of claim 16 , wherein one or more of the second fin and the third fin are curved.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title