Stud bump structure for semiconductor package assemblies

Patent metadata

Field	Value
Publication number	US-9768137-B2
Application number	US-201213460412-A
Country	US
Kind code	B2
Filing date	Apr 30, 2012
Priority date	Apr 30, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

First claim

What is claimed is:

1. A package structure, comprising:
a die bonded to a substrate, wherein the die has a first periphery region adjacent a first edge of the die and a second periphery region adjacent a second edge of the die opposing the first edge of the die, and a center region interposing the first and second periphery regions;
a plurality of stud bump structures connecting the die to the substrate, wherein each stud bump structure of the plurality of stud bump structures comprises a stud bump and a solder ball encapsulating the stud bump; and
a plurality of conductive structures connecting the die to the substrate, wherein each of the conductive structures is free of an encapsulating configuration,
wherein the plurality of stud bump structures and the plurality of conductive structures are arranged in a predetermined pattern wherein the plurality of stud bump structures are disposed within the first and second periphery regions of the die and the plurality of conductive structures are disposed in the center region of the die; and
an underfill between the die and the substrate.

2. The package structure of claim 1 , wherein a stud bump of the plurality of stud bump structures is connected to a bond pad.

3. The package structure of claim 1 , wherein a conductive structure of the plurality of conductive structures is a solder bump connecting the die to the substrate.

4. The package structure of claim 1 , wherein a conductive structure of the plurality of conductive structures is a copper pillar connecting the die to the substrate.

5. The package structure of claim 1 , wherein each stud bump of the plurality of stud bump structures has a material comprising aluminum, aluminum alloy, copper, copper alloy, gold, or gold alloy.

6. The package structure of claim 1 , wherein the underfill is disposed between the plurality of stud bump structures.

7. The package structure of claim 1 , wherein a first one of the plurality of stud bump structures connects the die to the substrate at a first corner of the die in the first periphery region and a second one of the plurality of stud bump structures connects the die to the substrate at a second corner of the die in the second periphery region.

8. A package on package structure, comprising:
a first substrate;
a first die bonded to the first substrate;
a second substrate disposed over the first die and bonded to the first substrate, such that the first die interposes the first and second substrates;
a second die bonded to the second substrate;
a plurality of first stud bump structures connecting the second substrate to the first substrate, wherein each first stud bump structure of the plurality of first stud bump structures comprises a stud bump disposed on a top surface of the first substrate and a solder ball encapsulating the stud bump, wherein the solder ball extends from the top surface of the first substrate to a bond pad disposed on a bottom surface of the second substrate; and
a plurality of conductive structures connecting the second substrate to the first substrate, wherein each conductive structure of the plurality of conductive structures is free of an encapsulating configuration,
wherein the plurality of first stud bump structures and the plurality of conductive structures are arranged in a predetermined pattern over the first substrate, wherein the predetermined pattern includes the plurality of first stud bump structures disposed adjacent a center-region of a lateral side of the first die and the plurality of conductive structures disposed adjacent a corner-region of the first die.

9. The package on package structure of claim 8 , wherein a stud bump of the plurality of first stud bump structures is connected to a bond pad.

10. The package on package structure of claim 8 , wherein the conductive structure is a solder bump connecting the second substrate to the first substrate.

11. The package on package structure of claim 8 , further comprising one or more copper pillars connecting the first die to the first substrate.

12. The package on package structure of claim 8 , wherein each stud bump of the plurality of first stud bump structures has a material comprising aluminum, aluminum alloy, copper, copper alloy, gold, or gold alloy.

13. The package on package structure of claim 8 , further comprising one or more second stud bump structures connected to an underside of the first substrate, wherein the one or more second stud bump structures comprise a stud bump and a solder ball encapsulating the stud bump.

14. A structure, comprising:
a member being a die or a substrate;
a plurality of stud bump structures on a surface of the member, each stud bump structure of the plurality of stud bump structures comprising:
a bond pad;
a conductive wire metallically connected to the bond pad, wherein the conductive wire forms a stud bump over the bond pad; and
a solder ball soldered to a top surface of the stud bump, the solder ball encapsulating the stud bump, wherein the solder ball has an exposed curvilinear surface over the top surface of the stud bump;

a solder bump on the surface of the member, wherein the solder bump is free of an encapsulating configuration; and
a moulding material around the plurality of stud bump structures and the solder bump.

15. The structure of claim 14 , wherein the conductive wire comprises aluminum, aluminum alloy, copper, copper alloy, gold, or gold alloy.

16. The structure of claim 14 , wherein the conductive wire comprises a lead-free conductor.

17. The structure of claim 14 , wherein the top of the stud bump forms a tail.

18. The package structure of claim 1 , wherein each stud bump of the plurality of stud bump structures has a material comprising aluminum or aluminum alloy.

Assignees

• Chen Meng-Tse
• Lin Hsiu-Jen
• Lin Chih-Wei
• Chen Cheng-Ting
• Cheng Ming-Da
• Liu Chung-Shi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Meng-Tse
• Lin Hsiu-Jen
• Lin Chih-Wei
• Chen Cheng-Ting
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title