Semiconductor device including three-dimensional crack detection structure

Patent metadata

Field	Value
Publication number	US-9768129-B2
Application number	US-201615200523-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Nov 2, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor device includes a semiconductor die, a semiconductor integrated circuit and a three-dimensional crack detection structure. The semiconductor die includes a central region and a peripheral region surrounding the central region. The semiconductor integrated circuit is formed in the central region. The three-dimensional crack detection structure is formed in a ring shape in the peripheral region to surround the central region. The three-dimensional crack detection structure is expanded in a vertical direction. Using the three-dimensional crack detection structure, the crack penetration of various types may be detected thoroughly.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor die including a central region and a peripheral region surrounding the central region;
a semiconductor integrated circuit formed in the central region; and
a three-dimensional crack detection structure formed in the peripheral region to surround the central region, the three-dimensional crack detection structure extending in a vertical direction that is perpendicular to a row direction and a column direction,
wherein the semiconductor die includes a first conduction layer and a second conduction layer below the first conduction layer,
wherein the three-dimensional crack detection structure includes a conduction loop that extends in the vertical direction between the first conduction layer and the second conduction layer,
wherein the conduction loop includes a plurality of top horizontal line segments formed in the first conduction layer, a plurality of bottom horizontal line segments formed in the second conduction layer, and a plurality of vertical line segments connecting the top horizontal line segments and the bottom horizontal line segments to form the conduction loop,
wherein the first conduction layer comprises a metal layer that is formed above a semiconductor substrate of the semiconductor die,
wherein the second conduction layer comprises a polysilicon layer that is formed between the semiconductor substrate and the metal layer, and
wherein each of the plurality of bottom horizontal line segments is shorter than each of the plurality of top horizontal line segments.

2. The semiconductor device of claim 1 , wherein the top horizontal line segments include metal line patterns formed in the metal layer,
wherein the bottom horizontal line segments include polysilicon line patterns formed in the polysilicon layer, and
wherein the vertical line segments include vertical contacts connecting the metal line patterns and the polysilicon line patterns to form the conduction loop.

3. The semiconductor device of claim 1 , wherein the first conduction layer comprises an uppermost metal layer among a plurality of metal layers that are formed above a semiconductor substrate of the semiconductor die.

4. The semiconductor device of claim 1 , wherein the second conduction layer comprises a gate polysilicon layer in which gates of transistors of a semiconductor integrated circuit are formed.

5. The semiconductor device of claim 1 , wherein the second conduction layer comprises a bitline polysilicon layer in which bitlines of a semiconductor integrated circuit are formed.

6. The semiconductor device of claim 1 , wherein the conduction loop includes at least one repeater configured to receive an input signal, amplify the input signal, and output an amplified signal.

7. A semiconductor device comprising:
a plurality of semiconductor dies stacked in a vertical direction, each of the semiconductor dies including a central region and a peripheral region surrounding the central region;
a plurality of semiconductor integrated circuits respectively formed in the central regions of the semiconductor dies; and
a three-dimensional crack detection structure formed in a ring shape in the peripheral regions of the semiconductor dies to surround the central regions, the three-dimensional crack detection structure extending in the vertical direction to cover the plurality of semiconductor dies,
wherein the three-dimensional crack detection structure comprises a conduction loop that includes a plurality of top horizontal line segments formed in an uppermost semiconductor die of the plurality of semiconductor dies, a plurality of bottom horizontal line segments formed in a lowermost semiconductor die of the plurality of semiconductor dies, and a plurality of vertical line segments each connecting a top horizontal line segment in the uppermost semiconductor die to a bottom horizontal line segment in the lowermost semiconductor die to form the conduction loop.

8. The semiconductor device of claim 7 , wherein the plurality of top horizontal line segments are formed in a first conduction layer of the uppermost semiconductor die, and
wherein the plurality of bottom horizontal line segments are formed in a second conduction layer of the lowermost semiconductor die.

9. A semiconductor device comprising:
a semiconductor die including a first conduction layer, a second conduction layer below the first conduction layer, a third conduction layer below the second conduction layer, and a central region and a peripheral region surrounding the central region;
a semiconductor integrated circuit formed in the central region; and
a three-dimensional crack detection structure formed in a ring shape in the peripheral region to surround the central region, the three-dimensional crack detection structure extending in a vertical direction that is perpendicular to a row direction and a column direction,
wherein the three-dimensional crack detection structure includes a first conduction loop that extends in the vertical direction between the second conduction layer and the third conduction layer and a second conduction loop formed in the first conduction layer.

10. The semiconductor device of claim 9 , wherein the first conduction loop includes:
a plurality of top horizontal line segments formed in the second conduction layer;
a plurality of bottom horizontal line segments formed in the third conduction layer; and
a plurality of vertical line segments connecting the top horizontal line segments and the bottom horizontal line segments to form the first conduction loop.

11. The semiconductor device of claim 10 , wherein the second conduction layer comprises a metal layer that is formed above a semiconductor substrate of the semiconductor die and the top horizontal line segments include metal line patterns formed in the metal layer, and
wherein the third conduction layer comprises a polysilicon layer that is formed between the semiconductor substrate and the metal layer and the bottom horizontal line segments include polysilicon line patterns formed in the polysilicon layer.

12. The semiconductor device of claim 11 , wherein the top horizontal line segments include metal line patterns formed in the metal layer,
wherein the bottom horizontal line segments include polysilicon line patterns formed in the polysilicon layer, and
wherein the vertical line segments include vertical contacts connecting the metal line patterns and the polysilicon line patterns to form the first conduction loop.

13. The semiconductor device of claim 12 , wherein each of the plurality of bottom horizontal line segments is shorter than each of the plurality of top horizontal line segments.

14. The semiconductor device of claim 9 , wherein the first conduction layer and the second conduction layer comprise metal layers that are formed above a semiconductor substrate of the semiconductor die, and
wherein the third conduction layer comprises a polysilicon layer that is formed between the semiconductor substrate and the metal layers.

15. The semiconductor device of claim 9 , wherein the first conduction layer and the second conduction layer respectively comprise first and second metal layers that are formed above a semiconductor substrate of the semiconductor die, and
wherein the third conduction layer comprises a third metal layer that is formed on a bottom surface of the semiconductor substrate.

16. The semiconductor device of claim 9 , wherein the second conduction layer comprises a metal layer that is formed above a semiconductor substrate of the semiconductor die, and
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seung-Seob
• Kwon Hyuk-Joon
• Lim Bo-Tak

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title