Semiconductor chip having plural penetration electrode penetrating therethrough

Patent metadata

Field	Value
Publication number	US-9466562-B2
Application number	US-201213720791-A
Country	US
Kind code	B2
Filing date	Dec 19, 2012
Priority date	Dec 22, 2011
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode.

First claim

What is claimed is:

1. A semiconductor device comprising at least one semiconductor chip, the semiconductor chip comprising:
a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the plurality of penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and
a wiring structure including at least one first wiring segment configured to intersect with a plurality of regions, each of the plurality of regions being defined as a region between a corresponding two of the first penetration electrodes, one end of the first wiring segment being electrically coupled to the second penetration electrode, the other end of the first wiring segment being electrically coupled to the third penetration electrode such that an electrical current flows between the second and third penetration electrodes through the first wiring segment of the wiring structure.

2. The semiconductor device as claimed in claim 1 , wherein the semiconductor chip further comprises a switch circuit and the other end of the wiring structure is coupled to the third penetration electrode through the switch circuit.

3. The semiconductor device as claimed in claim 1 , wherein the first penetration electrodes are arranged in matrix such that the plurality of regions are arranged in matrix.

4. The semiconductor device as claimed in claim 1 , wherein the wiring structure further includes at least one second wiring segment, the first wiring segment elongating in a first direction and the second wiring segment elongating in a second direction perpendicular to the first direction.

5. The semiconductor device as claimed in claim 4 , wherein the second wiring segment is configured not to intersect with any of the plurality of regions.

6. The semiconductor device as claimed in claim 4 , wherein each of the first and second wiring segments is configured to intersect with at least a corresponding one of the plurality of regions.

7. The semiconductor device as claimed in claim 1 , further comprising an additional semiconductor chip with which the semiconductor chip is stacked, the additional semiconductor chip including a plurality of additional penetration electrodes each electrically coupled to a corresponding one of the plurality of penetration electrodes of the semiconductor chip.

8. The semiconductor device as claimed in claim 7 , wherein the semiconductor chip is greater in size than the additional semiconductor chip.

9. The semiconductor device as claimed in claim 1 , wherein each of the penetration electrodes comprises:
a penetration plug penetrating a semiconductor substrate of the semiconductor chip; and
a multi-level wiring structure on the penetration plug, the multi-level wiring structure including a first pad as a lower level wiring coupled to the penetration plug and a second pad as an upper level wiring electrically coupled to the first pad;
the first wiring segment of the wiring structure is formed as the upper level wiring.

10. The semiconductor device as claimed in claim 4 , wherein each of the penetration electrodes comprises:
a penetration plug penetrating a semiconductor substrate of the semiconductor chip; and
a multi-level wiring structure on the penetration plug, the multi-level wiring structure including a first pad as a lower level wiring coupled to the penetration plug and a second pad as an upper level wiring electrically coupled to the first pad;
the first wiring segment of the wiring structure being formed as the lower level wiring and the second wiring segment of the wiring structure being formed as the upper level wiring.

11. A semiconductor device comprising at least one semiconductor chip, the semiconductor chip comprising:
a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the plurality of penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and
a wiring structure including a first terminal coupled to the second penetration electrode, a second terminal coupled to the third penetration electrode and a plurality of middle wirings coupled in series between the first and second terminals to make an electrical path between the second and third penetration electrodes, each of the middle wirings elongating such that each of the middle wirings threads its way through corresponding ones of the first penetration electrodes;
wherein the semiconductor chip is divided into first and second regions respectively including a plurality of memory cells and a third region sandwiched between the first and second regions, the third region being free from the memory cells, both the plurality of penetration electrodes and the wiring structure being arranged in the third region.

12. The semiconductor device as claimed in claim 11 , wherein the wiring structure comprises a single-level wiring structure and the middle wirings of the wiring structure are respectively formed as predetermined level wirings.

13. The semiconductor device as claimed in claim 12 , wherein the middle wirings are directly connected in series to each other.

14. The semiconductor device as claimed in claim 11 , wherein the wiring structure comprises a multi-level wiring structure, the middle wirings including one or more first middle wirings formed as lower level wirings and one or more second middle wirings formed as upper level wirings.

15. The semiconductor device as claimed in claim 14 , wherein the wiring structure further comprises one or more through electrodes each connecting a corresponding one of the first middle wirings and a corresponding one of the second middle wirings.

16. The semiconductor device as claimed in claim 11 , further comprising an additional semiconductor chip stacked with the semiconductor chip, the additional semiconductor chip comprising:
a plurality of additional penetration electrodes each penetrating between main and back surfaces of the additional semiconductor chip, the plurality of additional penetration electrodes including a plurality of additional first penetration electrodes respectively electrically coupled to the first penetration electrodes, an additional second penetration electrode electrically coupled to the second penetration electrode and an additional third penetration electrode electrically coupled to the third penetration electrode; and
an additional wiring structure including an additional first terminal coupled to the additional second penetration electrode, an additional second terminal coupled to the additional third penetration electrode and a plurality of additional middle wirings coupled in series between the additional first and additional second terminals to make an electrical path between the additional second and additional third penetration electrodes, each of the additional middle wirings elongating such that each of the additional middle wirings threads its way through corresponding ones of the additional first penetration electrodes.

17. The semiconductor device as claimed in claim 16 , wherein the semiconductor chip further includes a switch circuit coupled between the first terminal of the wiring structure and the second penetration electrode, the additional semiconductor chip further including an additional switch circuit coupled between the additional first terminal of the additional wiring structure and the additional second penetration electrode, the switch circuit and the additional switch

Assignees

• Ps4 Luxco Sarl

Inventors

• Nakazawa Shigeyuki
• Ishikawa Toru

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title