Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9768120-B2
Application number	US-201213683393-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

First claim

What is claimed is:

1. A semiconductor device assembly comprising:
a chip carrier;
a semiconductor die comprising a semiconductor portion and a conductive structure;
a soldered layer mechanically and electrically connecting the chip carrier and the conductive structure at a soldering side of the semiconductor die, wherein
at the soldering side an outermost surface portion of a rear side surface of the semiconductor portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion of the rear side surface, and
the conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion and connecting the central and outermost surface portions, and wherein the conductive structure comprises at least a conformal metal first sub-layer forming a barrier layer impermeable for copper ions and atoms and a second sub-layer from at least one of Ni, V, Au, Ag, W, Pt and Pd between the first sub-layer and the soldered layer, the first sub-layer covering the central surface portion, the intermediate surface portion and the outermost surface portion of the rear side surface, and the second sub-layer being present along the central surface portion and at least a portion of the intermediate surface portion and is absent along the outermost surface portion.

2. The semiconductor device assembly according to claim 1 , wherein
the central surface portion has a first distance and the outermost surface portion has a second distance to the chip carrier and a difference between the first and second distances is at least 10 μm.

3. The semiconductor device assembly according to claim 1 , wherein
the central and outermost surface portions are parallel.

4. The semiconductor device assembly according to claim 1 , wherein
the conductive structure is absent on the outermost surface portion.

5. The semiconductor device assembly according to claim 1 , wherein
the conductive structure is provided on the intermediate and outermost surface portions.

6. The semiconductor device according to claim 1 , wherein
the first sub-layer directly adjoins the semiconductor portion.

7. The semiconductor device according to claim 1 , wherein
the second sub-layer comprises NiV.

8. A semiconductor wafer comprising:
semiconductor dies arranged in a matrix, wherein each semiconductor die includes a conductive structure on a central die surface at a rear side of the semiconductor wafer, and
a kerf portion mechanically connecting the semiconductor dies and forming a rectangular grid with the semiconductor dies arranged in meshes of the grid, wherein
a lattice-like separation trench extends into the semiconductor wafer from the rear side between the central die surfaces, the separation trench being wider than the kerf portion, wherein
the conductive structure extends into the separation trench, and wherein the conductive structure comprises at least a conformal metal first sub-layer forming a barrier layer impermeable for copper ions and atoms and a second sub-layer from at least one of Ni, V, Au, Ag, W, Pt and Pd, wherein the first sub-layer is between the central die surface and the second sub-layer and the second sub-layer is absent along the bottom of the lattice-like separation trench.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Seng Philipp
• Hosseini Khalil
• Mauder Anton

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07353

  changes in shapes · CPC title

• H10W72/07336

  Soldering or alloying · CPC title