Top contact resistance measurement in vertical FETs

Patent metadata

Field	Value
Publication number	US-9768085-B1
Application number	US-201615218378-A
Country	US
Kind code	B1
Filing date	Jul 25, 2016
Priority date	Jul 25, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

First claim

What is claimed is:

1. A test device, comprising:
a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction;
a first portion of vertical transistors formed over the first dopant conductivity region as a device under test and a second portion of vertical transistors formed over the second dopant conductivity region; and
a common source/drain region formed over the first and second portions of vertical transistors;
wherein current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

2. The device as recited in claim 1 , wherein the vertical transistors are formed vertically along semiconductor fins such that a device channel for the vertical transistors is disposed in a normal direction relative to the diode junction layer.

3. The device as recited in claim 2 , wherein the first portion of vertical transistors includes whole fins.

4. The device as recited in claim 2 , wherein the first portion of vertical transistors includes part of fins that extends into a device under test region and part that extends into a test setup region outside the device under test region.

5. The device as recited in claim 1 , further comprising a common gate structure that serves both the first and second portions of vertical transistors.

6. The device as recited in claim 1 , wherein the diode junction actively prevents lateral current flow in the common source/drain region to measure sense potential.

7. The device as recited in claim 6 , wherein a source voltage of the device under s is maintained at substantially zero to measure the sense potential.

8. A test device, comprising:
a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction, the first dopant conductivity region including a vertical transistor drain for a device under test;
a first portion of vertical transistors formed over the first dopant conductivity region as the device under test and a second portion of vertical transistors formed over the second dopant conductivity region, wherein the vertical transistors are formed vertically along semiconductor fins such that a device channel for the vertical transistors is disposed in a normal direction relative to the diode junction layer; and
a common source/drain region formed over the first and second portions of vertical transistors, the common source/drain region including a vertical transistor source for the device under test, wherein current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

9. The device as recited in claim 8 , wherein the first portion of vertical transistors includes whole fins.

10. The device as recited in claim 8 , wherein the first portion of vertical transistors includes part of fins that extends into a device under test region and part that extends into a test setup region outside the device under test region.

11. The device as recited in claim 8 , further comprising a common gate structure that serves both the first and second portions of vertical transistors.

12. The device as recited in claim 8 , wherein the diode junction actively prevents lateral current flow in the common source/drain region to measure sense potential.

13. The device as recited in claim 12 , wherein a source voltage of the device under test is maintained at substantially zero to measure the sense potential.

14. The device as recited in claim 8 , further comprising a drain contact formed on the drain, a source contact formed on a device under test side of the common source/drain region and the probe contact formed on a test setup side of the common source/drain region.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Liu Zuoguang
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• G01R31/2813

  Checking the presence, location, orientation or value, e.g. resistance, of components or conductors (orientation of the DUT with respect to the test fixture G01R1/06705) · CPC title