Buried fin contact structures on FinFET semiconductor devices

Patent metadata

Field	Value
Publication number	US-9362403-B2
Application number	US-201514817628-A
Country	US
Kind code	B2
Filing date	Aug 4, 2015
Priority date	Sep 4, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.

First claim

What is claimed is:

1. A device, comprising:
at least one fin defined in a semiconductor substrate;
a raised isolation structure with a recess formed therein, wherein said raised isolation structure has an upper surface, a bottom surface that is positioned below said upper surface and an interior perimeter surface;
a gate structure positioned around at least a portion of said at least one fin, wherein said upper surface of said raised isolation structure is positioned at a height below an upper surface of said gate structure;
a plurality of spaced-apart buried fin contact structures positioned within said recess and covering an entirety of said bottom surface, wherein each of said buried fin contact structures is positioned on opposite sides of said gate structure and wherein each of said buried fin contact structures contacts at least a portion of a sidewall of said at least one fin and a top surface of said at least one fin and has an upper surface that is positioned level with or below said upper surface of said raised isolation structure and above said top surface of said at least one fin;
at least one layer of insulating material positioned above said plurality of buried fin contact structures and said raised isolation structure; and
a plurality of source/drain contact structures positioned in said at least one layer of insulating material, wherein each of said source/drain contact structures is conductively coupled to one of said plurality of buried fin contact structures.

2. The device of claim 1 , wherein each of said buried fin contact structures further comprises an outer perimeter surface and wherein at least a portion of said outer perimeter surface of each of said buried fin contact structures contacts at least a portion of said interior perimeter surface of said raised isolation structure.

3. The device of claim 2 , wherein said exterior perimeter surface of each of said buried fin contact structures contacts said interior perimeter surface of said raised isolation structure and a sidewall spacer formed adjacent opposite sides of said gate structure.

4. The device of claim 1 , wherein said plurality of source/drain contact structures are post-type source/drain contact structures.

5. The device of claim 1 , wherein each of said plurality of buried fin contact structures has a substantially planar upper surface.

6. The device of claim 1 , wherein said gate structure is one of a replacement gate structure or a gate-first gate structure.

7. The device of claim 1 , wherein said bottom surface of said raised isolation structure is positioned under a portion of said gate structure.

8. A device, comprising:
at least one fin defined in a semiconductor substrate;
a raised isolation structure with a recess formed therein, wherein said raised isolation structure has an upper surface, a substantially planar bottom surface that is positioned at a level that is below a level of said upper surface and an interior perimeter surface;
a gate structure positioned around at least a portion of said at least one fin, wherein said upper surface of said raised isolation structure is positioned at a height below an upper surface of said gate structure;
a plurality of spaced-apart buried fin contact structures positioned within said recess and covering an entirety of said bottom surface, wherein each of said buried fin contact structures is positioned on opposite sides of said gate structure and wherein each of said buried fin contact structures contacts at least a portion of a sidewall of said at least one fin and a top surface of said at least one fin and has a substantially planar upper surface that is positioned level with or below said upper surface of said raised isolation structure and above said top surface of said at least one fin;
at least one layer of insulating material positioned above said plurality of buried fin contact structures and said raised isolation structure; and
a plurality of source/drain contact structures positioned in said at least one layer of insulating material, wherein each of said source/drain contact structures is conductively coupled to one of said plurality of buried fin contact structures.

9. The device of claim 8 , wherein each of said buried fin contact structures further comprises an outer perimeter surface and wherein a portion of said outer perimeter surface of each of said buried fin contact structures contacts a portion of said interior perimeter surface of said raised isolation structure.

10. The device of claim 8 , wherein said exterior perimeter surface of a first of said buried fin contact structures contacts and engages said interior perimeter surface of said raised isolation structure and a sidewall spacer formed adjacent a first side of said gate structure, and a second of said buried fin contact structures contacts and engages said interior perimeter surface of said raised isolation structure and a sidewall spacer formed adjacent a second side of said gate structure.

11. The device of claim 10 , wherein said plurality of source/drain contact structures are post-type source/drain contact structures.

12. The device of claim 11 , wherein said gate structure is one of a replacement gate structure or a gate-first gate structure.

13. The device of claim 8 , wherein said substantially planar bottom surface of said raised isolation structure is positioned under a portion of said gate structure.

14. A device, comprising:
at least one fin defined in a semiconductor substrate;
a raised isolation structure with a recess formed therein, wherein said raised isolation structure has an upper surface, a substantially planar bottom surface that is positioned at a level that is below a level of said upper surface and an interior perimeter surface;
a gate structure positioned around at least a portion of said at least one fin, wherein said upper surface of said raised isolation structure is positioned at a height below an upper surface of said gate structure;
a sidewall spacer positioned adjacent first and second sides of said gate structure;
first and second spaced-apart buried fin contact structures positioned within said recess and covering an entirety of said bottom surface, wherein said first and second buried fin contact structures are positioned adjacent first and second sides, respectively, of said gate structure and wherein each of said first and second buried fin contact structures contacts at least a portion of a sidewall of said at least one fin and a top surface of said at least one fin and has a substantially planar upper surface that is positioned level with or below said upper surface of said raised isolation structure and above said top surface of said at least one fin, wherein each of said first and second buried fin contact structures further comprises an outer perimeter surface that contacts and engages a first portion of said interior perimeter surface of said raised isolation structure and a portion of said sidewall spacer formed adjacent said first side of said gate structure, and said second buried fin contact structure contacts and engages a second portion of said interior perimeter surface of said raised isolation structure and a portion of said sidewall spacer formed adjacent said second side of said gate structure;
at least one layer of insulating material positioned above said first and second buried fin contact structures and said raised isolation structure; and
a plurality of source/drain contact structures positioned in said at least one layer of insulating material, wherein each of said source/drain contact structures is conductively coupled to one of said first and second buried

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Kim Ryan Ryoung-Han
• Taylor Jr William J

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/113

  Isolations within a component, i.e. internal isolations · CPC title