Power semiconductor substrates with metal contact layer and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9768036-B2
Application number	US-15202108-A
Country	US
Kind code	B2
Filing date	May 12, 2008
Priority date	May 12, 2007
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.

First claim

What is claimed is:

1. A substrate for supporting a power semiconductor, the substrate comprising:
an insulating planar base;
at least one conductor track having at least one contact area; and
a layer of a metallic material disposed on top of said contact area and electrically connected thereto by a pressure sinter connection, said metallic material not being sintered to the power semiconductor, and being the uppermost layer of the substrate forming a contact surface for electrical connection, said contact surface being separate from said power semiconductor.

2. The power semiconductor substrate of claim 1 , wherein said layer of metallic material is at least 10 micrometers thick and has a proportion of more than 90 percent of a noble metal.

3. The power semiconductor substrate of claim 2 , wherein said noble metal is silver.

4. The power semiconductor substrate of claim 1 , further comprising a second metallic layer of a noble metal having a layer thickness of no more than fifteen atomic layers disposed between said contact area and said layer of metallic material.

5. A method for producing a substrate for supporting a power semiconductor, comprising the steps of:
producing a power semiconductor substrate including a planar insulating base and at least one conductor track having at least one contact area;
arranging a top pasty layer composed of a metallic material and a solvent, on at least one of said contact areas, but not on the power semiconductor; and
applying pressure to said pasty layer, and thereby sintering said metallic material to said at least one of said contact areas, but not to said power semiconductor;
whereby said sintered metallic material becomes the uppermost layer of the substrate forming a contact surface for electrical connection, said contact surface being separate from said power semiconductor.

6. The method of claim 5 , wherein said pasty layer is applied by means of a stencil printing method.

7. The method of claim 5 , wherein said pressure is applied by means of a press and two pressing rams, wherein at least one pressing ram is formed with a quasi-hydrostatic pressure generating silicone pad arranged thereon.

8. The method of claim 5 , wherein the maximum end pressure applied to said pasty layer is at least 8 MPa.

9. The method of claim 5 , further comprising the step of heating said power semiconductor substrate to at least about 350° K during the application of pressure thereto.

10. The method of claim 5 , further comprising the step of covering said power semiconductor substrate with a film prior to the application of pressure thereto.

Assignees

• Göbl Christian
• Braml Heiko
• Semikron Elektronik Gmbh & Co Kg

Inventors

• Göbl Christian
• Braml Heiko

Classifications

• C04B2237/124

  based on copper · CPC title

• H05K2203/0191

  Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste · CPC title

• H05K2203/1131

  Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity · CPC title

• H05K3/06

  the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} · CPC title

• H05K2201/0133

  Elastomeric or compliant polymer · CPC title